| /kernel/linux/linux-4.19/drivers/isdn/hisax/ |
| D | callc.c | 38 /* Value to delay the sending of the first B-channel packet after CONNECT
62 if (cards[i].cs) in hisax_findcard()
63 if (cards[i].cs->myid == driverid) in hisax_findcard()
64 return (cards[i].cs); in hisax_findcard()
75 sprintf(tmp, "Ch%d %s ", chanp->chan, in link_debug()
76 direction ? "LL->HL" : "HL->LL"); in link_debug()
77 VHiSax_putstatus(chanp->cs, tmp, fmt, args); in link_debug()
87 ST_WAIT_BCONN, /* 5 CONNECT/CONN_ACK received, awaiting b-channel prot. estbl. */
178 ic.driver = chanp->cs->myid; in HL_LL()
180 ic.arg = chanp->chan; in HL_LL()
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/memory-controllers/ |
| D | omap-gpmc.txt | 7 - compatible: Should be set to one of the following:
9 ti,omap2420-gpmc (omap2420)
10 ti,omap2430-gpmc (omap2430)
11 ti,omap3430-gpmc (omap3430 & omap3630)
12 ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
13 ti,am3352-gpmc (am335x devices)
15 - reg: A resource specifier for the register space
17 - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
19 - #address-cells: Must be set to 2 to allow memory address translation
20 - #size-cells: Must be set to 1 to allow CS address passing
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | omap-gpmc.txt | 7 - compatible: Should be set to one of the following:
9 ti,omap2420-gpmc (omap2420)
10 ti,omap2430-gpmc (omap2430)
11 ti,omap3430-gpmc (omap3430 & omap3630)
12 ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
13 ti,am3352-gpmc (am335x devices)
15 - reg: A resource specifier for the register space
17 - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
19 - #address-cells: Must be set to 2 to allow memory address translation
20 - #size-cells: Must be set to 1 to allow CS address passing
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/spi/ |
| D | spi-fsl-dspi.txt | 4 - compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
5 "fsl,ls2085a-dspi"
7 "fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
8 "fsl,ls1012a-dspi" followed by "fsl,ls1021a-v1.0-dspi"
9 - reg : Offset and length of the register set for the device
10 - interrupts : Should contain SPI controller interrupt
11 - clocks: from common clock binding: handle to dspi clock.
12 - clock-names: from common clock binding: Shall be "dspi".
13 - pinctrl-0: pin control group to be used for this controller.
14 - pinctrl-names: must contain a "default" entry.
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| D | spi-dw.txt | 4 - compatible: should be "snps,designware-spi"
5 - #address-cells: see spi-bus.txt
6 - #size-cells: see spi-bus.txt
7 - reg: address and length of the spi master registers
8 - interrupts: should contain one interrupt
9 - clocks: spi clock phandle
10 - num-cs: see spi-bus.txt
13 - cs-gpios: see spi-bus.txt
18 compatible = "snps,designware-spi";
22 num-cs = <2>;
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| D | spi-lantiq-ssc.txt | 4 - compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi"
5 - #address-cells: see spi-bus.txt
6 - #size-cells: see spi-bus.txt
7 - reg: address and length of the spi master registers
8 - interrupts: should contain the "spi_rx", "spi_tx" and "spi_err" interrupt.
12 - clocks: spi clock phandle
13 - num-cs: see spi-bus.txt, set to 8 if unset
14 - base-cs: the number of the first chip select, set to 1 if unset.
20 compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi";
22 interrupt-parent = <&icu0>;
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| D | omap-spi.txt | 4 - compatible :
5 - "ti,omap2-mcspi" for OMAP2 & OMAP3.
6 - "ti,omap4-mcspi" for OMAP4+.
7 - ti,spi-num-cs : Number of chipselect supported by the instance.
8 - ti,hwmods: Name of the hwmod associated to the McSPI
9 - ti,pindir-d0-out-d1-in: Select the D0 pin as output and D1 as
14 - dmas: List of DMA specifiers with the controller specific format
17 - dma-names: List of DMA request names. These strings correspond
27 #address-cells = <1>;
28 #size-cells = <0>;
[all …]
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| D | spi-cadence.txt | 2 -------------------------------------------
5 - compatible : Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6".
6 - reg : Physical base address and size of SPI registers map.
7 - interrupts : Property with a value describing the interrupt
9 - clock-names : List of input clock names - "ref_clk", "pclk"
11 - clocks : Clock phandles (see clock bindings for details).
14 - num-cs : Number of chip selects used.
17 - is-decoded-cs : Flag to indicate whether decoder is used or not.
22 compatible = "xlnx,zynq-spi-r1p6";
23 clock-names = "ref_clk", "pclk";
[all …]
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| D | snps,dw-apb-ssi.txt | 4 - compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
6 - reg : The register base for the controller. For "mscc,<soc>-spi", a second
8 - interrupts : One interrupt, used by the controller.
9 - #address-cells : <1>, as required by generic SPI binding.
10 - #size-cells : <0>, also as required by generic SPI binding.
13 - cs-gpios : Specifies the gpio pis to be used for chipselects.
14 - num-cs : The number of chipselects. If omitted, this will default to 4.
15 - reg-io-width : The I/O register width (in bytes) implemented by this
23 compatible = "snps,dw-apb-ssi";
26 #address-cells = <1>;
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| D | spi-bcm63xx.txt | 4 - compatible: must contain one of "brcm,bcm6348-spi", "brcm,bcm6358-spi".
5 - reg: Base address and size of the controllers memory area.
6 - interrupts: Interrupt for the SPI block.
7 - clocks: phandle of the SPI clock.
8 - clock-names: has to be "spi".
9 - #address-cells: <1>, as required by generic SPI binding.
10 - #size-cells: <0>, also as required by generic SPI binding.
13 - num-cs: some controllers have less than 8 cs signals. Defaults to 8
21 compatible = "brcm,bcm6368-spi", "brcm,bcm6358-spi";
27 clock-names = "spi";
[all …]
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| D | spi-bcm63xx-hsspi.txt | 4 - compatible: must contain of "brcm,bcm6328-hsspi".
5 - reg: Base address and size of the controllers memory area.
6 - interrupts: Interrupt for the SPI block.
7 - clocks: phandles of the SPI clock and the PLL clock.
8 - clock-names: must be "hsspi", "pll".
9 - #address-cells: <1>, as required by generic SPI binding.
10 - #size-cells: <0>, also as required by generic SPI binding.
13 - num-cs: some controllers have less than 8 cs signals. Defaults to 8
21 compatible = "brcm,bcm6328-hsspi";
27 clock-names = "hsspi", "pll";
[all …]
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| D | spi-gpio.txt | 1 SPI-GPIO devicetree bindings
3 This represents a group of 3-n GPIO lines used for bit-banged SPI on dedicated
8 - compatible: should be set to "spi-gpio"
9 - #address-cells: should be set to <0x1>
10 - ranges
11 - sck-gpios: GPIO spec for the SCK line to use
12 - miso-gpios: GPIO spec for the MISO line to use
13 - mosi-gpios: GPIO spec for the MOSI line to use
14 - cs-gpios: GPIOs to use for chipselect lines.
15 Not needed if num-chipselects = <0>.
[all …]
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| D | spi-rspi.txt | 4 - compatible : For Renesas Serial Peripheral Interface on legacy SH:
5 "renesas,rspi-<soctype>", "renesas,rspi" as fallback.
7 "renesas,rspi-<soctype>", "renesas,rspi-rz" as fallback.
8 For Quad Serial Peripheral Interface on R-Car Gen2 and
10 "renesas,qspi-<soctype>", "renesas,qspi" as fallback.
12 - "renesas,rspi-sh7757" (SH)
13 - "renesas,rspi-r7s72100" (RZ/A1H)
14 - "renesas,qspi-r8a7743" (RZ/G1M)
15 - "renesas,qspi-r8a7745" (RZ/G1E)
16 - "renesas,qspi-r8a7790" (R-Car H2)
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/ |
| D | spi-fsl-dspi.txt | 4 - compatible : must be one of:
5 "fsl,vf610-dspi",
6 "fsl,ls1021a-v1.0-dspi",
7 "fsl,ls1012a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
8 "fsl,ls1028a-dspi",
9 "fsl,ls1043a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
10 "fsl,ls1046a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
11 "fsl,ls1088a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
12 "fsl,ls2080a-dspi" (optionally followed by "fsl,ls2085a-dspi"),
13 "fsl,ls2085a-dspi",
[all …]
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| D | omap-spi.txt | 4 - compatible :
5 - "ti,am654-mcspi" for AM654.
6 - "ti,omap2-mcspi" for OMAP2 & OMAP3.
7 - "ti,omap4-mcspi" for OMAP4+.
8 - ti,spi-num-cs : Number of chipselect supported by the instance.
9 - ti,hwmods: Name of the hwmod associated to the McSPI
10 - ti,pindir-d0-out-d1-in: Select the D0 pin as output and D1 as
15 - dmas: List of DMA specifiers with the controller specific format
18 - dma-names: List of DMA request names. These strings correspond
28 #address-cells = <1>;
[all …]
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| D | spi-cadence.txt | 2 -------------------------------------------
5 - compatible : Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6".
6 - reg : Physical base address and size of SPI registers map.
7 - interrupts : Property with a value describing the interrupt
9 - clock-names : List of input clock names - "ref_clk", "pclk"
11 - clocks : Clock phandles (see clock bindings for details).
14 - num-cs : Number of chip selects used.
17 - is-decoded-cs : Flag to indicate whether decoder is used or not.
22 compatible = "xlnx,zynq-spi-r1p6";
23 clock-names = "ref_clk", "pclk";
[all …]
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| D | spi-lantiq-ssc.txt | 4 - compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi",
5 "intel,lgm-spi"
6 - #address-cells: see spi-bus.txt
7 - #size-cells: see spi-bus.txt
8 - reg: address and length of the spi master registers
9 - interrupts:
10 For compatible "intel,lgm-ssc" - the common interrupt number for
18 - clocks: spi clock phandle
19 - num-cs: see spi-bus.txt, set to 8 if unset
20 - base-cs: the number of the first chip select, set to 1 if unset.
[all …]
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| D | spi-bcm63xx.txt | 4 - compatible: must contain one of "brcm,bcm6348-spi", "brcm,bcm6358-spi".
5 - reg: Base address and size of the controllers memory area.
6 - interrupts: Interrupt for the SPI block.
7 - clocks: phandle of the SPI clock.
8 - clock-names: has to be "spi".
9 - #address-cells: <1>, as required by generic SPI binding.
10 - #size-cells: <0>, also as required by generic SPI binding.
13 - num-cs: some controllers have less than 8 cs signals. Defaults to 8
21 compatible = "brcm,bcm6368-spi", "brcm,bcm6358-spi";
27 clock-names = "spi";
[all …]
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| D | spi-bcm63xx-hsspi.txt | 4 - compatible: must contain of "brcm,bcm6328-hsspi".
5 - reg: Base address and size of the controllers memory area.
6 - interrupts: Interrupt for the SPI block.
7 - clocks: phandles of the SPI clock and the PLL clock.
8 - clock-names: must be "hsspi", "pll".
9 - #address-cells: <1>, as required by generic SPI binding.
10 - #size-cells: <0>, also as required by generic SPI binding.
13 - num-cs: some controllers have less than 8 cs signals. Defaults to 8
21 compatible = "brcm,bcm6328-hsspi";
27 clock-names = "hsspi", "pll";
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| D | spi-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-GPIO devicetree bindings
10 - Rob Herring <robh@kernel.org>
13 This represents a group of 3-n GPIO lines used for bit-banged SPI on
17 - $ref: "/schemas/spi/spi-controller.yaml#"
21 const: spi-gpio
23 sck-gpios:
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| /kernel/linux/linux-5.10/drivers/net/ethernet/pasemi/ |
| D | pasemi_mac.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and
78 struct pasemi_mac_csring *cs[MAX_CS]; member
94 #define TX_DESC(tx, num) ((tx)->chan.ring_virt[(num) & (TX_RING_SIZE-1)]) argument
95 #define TX_DESC_INFO(tx, num) ((tx)->ring_info[(num) & (TX_RING_SIZE-1)]) argument
96 #define RX_DESC(rx, num) ((rx)->chan.ring_virt[(num) & (RX_RING_SIZE-1)]) argument
97 #define RX_DESC_INFO(rx, num) ((rx)->ring_info[(num) & (RX_RING_SIZE-1)]) argument
98 #define RX_BUFF(rx, num) ((rx)->buffers[(num) & (RX_RING_SIZE-1)]) argument
99 #define CS_DESC(cs, num) ((cs)->chan.ring_virt[(num) & (CS_RING_SIZE-1)]) argument
101 #define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \
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| /kernel/linux/linux-4.19/fs/fuse/ |
| D | dev.c | 3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
33 * Lockless access is OK, because file->private data is set in fuse_get_dev()
36 return READ_ONCE(file->private_data); in fuse_get_dev()
46 INIT_LIST_HEAD(&req->list); in fuse_request_init()
47 INIT_LIST_HEAD(&req->intr_entry); in fuse_request_init()
48 init_waitqueue_head(&req->waitq); in fuse_request_init()
49 refcount_set(&req->count, 1); in fuse_request_init()
50 req->pages = pages; in fuse_request_init()
51 req->page_descs = page_descs; in fuse_request_init()
52 req->max_pages = npages; in fuse_request_init()
[all …]
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| /kernel/linux/linux-5.10/fs/fuse/ |
| D | dev.c | 3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
37 * Lockless access is OK, because file->private data is set in fuse_get_dev()
40 return READ_ONCE(file->private_data); in fuse_get_dev()
45 INIT_LIST_HEAD(&req->list); in fuse_request_init()
46 INIT_LIST_HEAD(&req->intr_entry); in fuse_request_init()
47 init_waitqueue_head(&req->waitq); in fuse_request_init()
48 refcount_set(&req->count, 1); in fuse_request_init()
49 __set_bit(FR_PENDING, &req->flags); in fuse_request_init()
50 req->fm = fm; in fuse_request_init()
69 refcount_inc(&req->count); in __fuse_get_request()
[all …]
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| /kernel/linux/linux-4.19/drivers/net/ethernet/pasemi/ |
| D | pasemi_mac.h | 4 * Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and
89 struct pasemi_mac_csring *cs[MAX_CS]; member
105 #define TX_DESC(tx, num) ((tx)->chan.ring_virt[(num) & (TX_RING_SIZE-1)]) argument
106 #define TX_DESC_INFO(tx, num) ((tx)->ring_info[(num) & (TX_RING_SIZE-1)]) argument
107 #define RX_DESC(rx, num) ((rx)->chan.ring_virt[(num) & (RX_RING_SIZE-1)]) argument
108 #define RX_DESC_INFO(rx, num) ((rx)->ring_info[(num) & (RX_RING_SIZE-1)]) argument
109 #define RX_BUFF(rx, num) ((rx)->buffers[(num) & (RX_RING_SIZE-1)]) argument
110 #define CS_DESC(cs, num) ((cs)->chan.ring_virt[(num) & (CS_RING_SIZE-1)]) argument
112 #define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \
113 & ((ring)->size - 1))
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/toshiba/ |
| D | tmpv7708.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * (C) Copyright 2018 - 2020, Toshiba Corporation.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
17 #address-cells = <2>;
18 #size-cells = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu-map {
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