| /kernel/linux/linux-5.10/drivers/pci/controller/ |
| D | pcie-rcar-ep.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe endpoint driver for Renesas R-Car SoCs
6 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
16 #include <linux/pci-epc.h>
20 #include "pcie-rcar.h"
24 /* Structure representing the PCIe interface */
26 struct rcar_pcie pcie; member
36 static void rcar_pcie_ep_hw_init(struct rcar_pcie *pcie) in rcar_pcie_ep_hw_init() argument
40 rcar_pci_write_reg(pcie, 0, PCIETCTLR); in rcar_pcie_ep_hw_init()
43 rcar_pci_write_reg(pcie, 0, PCIEMSR); in rcar_pcie_ep_hw_init()
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| D | pcie-rockchip-ep.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Rockchip AXI PCIe endpoint controller driver
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
15 #include <linux/pci-epc.h>
17 #include <linux/pci-epf.h>
20 #include "pcie-rockchip.h"
23 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
24 * @rockchip: Rockchip PCIe controller
33 * IRQ) TLP through the PCIe bus.
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| /kernel/linux/linux-5.10/drivers/pci/controller/cadence/ |
| D | pcie-cadence-ep.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe endpoint controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
9 #include <linux/pci-epc.h>
13 #include "pcie-cadence.h"
22 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); in cdns_pcie_ep_write_header() local
23 struct cdns_pcie *pcie = &ep->pcie; in cdns_pcie_ep_write_header() local
25 cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); in cdns_pcie_ep_write_header()
26 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); in cdns_pcie_ep_write_header()
27 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code); in cdns_pcie_ep_write_header()
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| D | pcie-cadence-plat.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Cadence PCIe platform driver.
14 #include "pcie-cadence.h"
19 * struct cdns_plat_pcie - private data for this PCIe platform driver
20 * @pcie: Cadence PCIe controller
21 * @is_rc: Set to 1 indicates the PCIe controller mode is Root Complex,
25 struct cdns_pcie *pcie; member
35 static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) in cdns_plat_cpu_addr_fixup() argument
49 struct device *dev = &pdev->dev; in cdns_plat_pcie_probe()
51 struct cdns_pcie_ep *ep; in cdns_plat_pcie_probe() local
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| D | pci-j721e.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
22 #include "pcie-cadence.h"
74 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_user_readl() argument
76 return readl(pcie->user_cfg_base + offset); in j721e_pcie_user_readl()
79 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, in j721e_pcie_user_writel() argument
82 writel(value, pcie->user_cfg_base + offset); in j721e_pcie_user_writel()
85 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_intd_readl() argument
87 return readl(pcie->intd_cfg_base + offset); in j721e_pcie_intd_readl()
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| /kernel/linux/linux-4.19/drivers/pci/controller/ |
| D | pcie-cadence-ep.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe endpoint controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
9 #include <linux/pci-epc.h>
14 #include "pcie-cadence.h"
21 * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver
22 * @pcie: Cadence PCIe controller
30 * IRQ) TLP through the PCIe bus.
38 struct cdns_pcie pcie; member
52 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); in cdns_pcie_ep_write_header() local
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| D | pcie-rockchip-ep.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Rockchip AXI PCIe endpoint controller driver
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
15 #include <linux/pci-epc.h>
17 #include <linux/pci-epf.h>
20 #include "pcie-rockchip.h"
23 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
24 * @rockchip: Rockchip PCIe controller
32 * IRQ) TLP through the PCIe bus.
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| /kernel/linux/linux-5.10/drivers/pci/controller/dwc/ |
| D | pci-layerscape-ep.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe controller EP driver for Freescale Layerscape SoCs
19 #include "pcie-designware.h"
23 #define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
47 ls_pcie_ep_get_features(struct dw_pcie_ep *ep) in ls_pcie_ep_get_features() argument
49 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in ls_pcie_ep_get_features()
50 struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci); in ls_pcie_ep_get_features() local
52 return pcie->ls_epc; in ls_pcie_ep_get_features()
55 static void ls_pcie_ep_init(struct dw_pcie_ep *ep) in ls_pcie_ep_init() argument
57 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in ls_pcie_ep_init()
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| D | pci-exynos.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Samsung Exynos SoCs
26 #include "pcie-designware.h"
28 #define to_exynos_pcie(x) dev_get_drvdata((x)->dev)
30 /* PCIe ELBI registers */
56 void __iomem *elbi_base; /* DT 0th resource: PCIe CTRL */
76 struct exynos_pcie *ep);
77 int (*get_clk_resources)(struct exynos_pcie *ep);
78 int (*init_clk_resources)(struct exynos_pcie *ep);
79 void (*deinit_clk_resources)(struct exynos_pcie *ep);
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
23 bool "TI DRA7xx PCIe controller Host Mode"
31 Enables support for the PCIe controller in the DRA7xx SoC to work in
32 host mode. There are two instances of PCIe controller in DRA7xx.
33 This controller can work either as EP or RC. In order to enable
34 host-specific features PCI_DRA7XX_HOST must be selected and in order
35 to enable device-specific features PCI_DRA7XX_EP must be selected.
39 bool "TI DRA7xx PCIe controller Endpoint Mode"
46 Enables support for the PCIe controller in the DRA7xx SoC to work in
47 endpoint mode. There are two instances of PCIe controller in DRA7xx.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | rcar-pci-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car PCIe Endpoint
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
12 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
17 - enum:
18 - renesas,r8a774a1-pcie-ep # RZ/G2M
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| D | layerscape-pci.txt | 1 Freescale Layerscape PCIe controller
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
7 which is used to describe the PLL settings at the time of chip-reset.
10 register available in the Freescale PCIe controller register set,
11 which can allow determining the underlying DesignWare PCIe controller version
15 - compatible: should contain the platform identifier such as:
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
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| D | ti-pci.txt | 3 PCIe DesignWare Controller
4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
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| D | cdns,cdns-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence PCIe EP Controller
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: "cdns-pcie-ep.yaml#"
14 - $ref: "pci-ep.yaml#"
18 const: cdns,cdns-pcie-ep
23 reg-names:
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| D | ti,j721e-pci-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI J721E PCI EP (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: "cdns-pcie-ep.yaml#"
19 - ti,j721e-pcie-ep
24 reg-names:
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| D | pci-keystone.txt | 1 TI Keystone PCIe interface
4 hardware version 3.65. It shares common functions with the PCIe DesignWare
6 Documentation/devicetree/bindings/pci/designware-pcie.txt
8 Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
12 Required Properties:-
14 compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
15 Should be "ti,am654-pcie-rc" for RC on AM654x SoC
16 reg: Three register ranges as listed in the reg-names property
17 reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
22 interrupt-cells: should be set to 1
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| D | socionext,uniphier-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe endpoint controller
10 UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/designware-pcie.txt.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - $ref: "pci-ep.yaml#"
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| D | axis,artpec6-pcie.txt | 1 * Axis ARTPEC-6 PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
7 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
11 - reg: base addresses and lengths of the PCIe controller (DBI),
13 - reg-names: Must include the following entries:
14 - "dbi"
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| D | designware-pcie.txt | 1 * Synopsys DesignWare PCIe interface
4 - compatible:
5 "snps,dw-pcie" for RC mode;
6 "snps,dw-pcie-ep" for EP mode;
7 - reg: For designware cores version < 4.80 contains the configuration
10 - reg-names: Must be "config" for the PCIe configuration space and "atu" for
15 - #address-cells: set to <3>
16 - #size-cells: set to <2>
17 - device_type: set to "pci"
18 - ranges: ranges for the PCI memory and I/O regions
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| /kernel/linux/linux-4.19/drivers/pci/controller/dwc/ |
| D | pci-exynos.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Samsung EXYNOS SoCs
26 #include "pcie-designware.h"
28 #define to_exynos_pcie(x) dev_get_drvdata((x)->dev)
30 /* PCIe ELBI registers */
56 void __iomem *elbi_base; /* DT 0th resource: PCIe CTRL */
76 struct exynos_pcie *ep);
77 int (*get_clk_resources)(struct exynos_pcie *ep);
78 int (*init_clk_resources)(struct exynos_pcie *ep);
79 void (*deinit_clk_resources)(struct exynos_pcie *ep);
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/pci/ |
| D | designware-pcie.txt | 1 * Synopsys DesignWare PCIe interface
4 - compatible:
5 "snps,dw-pcie" for RC mode;
6 "snps,dw-pcie-ep" for EP mode;
7 - reg: Should contain the configuration address space.
8 - reg-names: Must be "config" for the PCIe configuration space.
11 - num-lanes: number of lanes to use
13 - #address-cells: set to <3>
14 - #size-cells: set to <2>
15 - device_type: set to "pci"
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| D | axis,artpec6-pcie.txt | 1 * Axis ARTPEC-6 PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
7 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
11 - reg: base addresses and lengths of the PCIe controller (DBI),
13 - reg-names: Must include the following entries:
14 - "dbi"
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| D | ti-pci.txt | 3 PCIe DesignWare Controller
4 - compatible: Should be "ti,dra7-pcie" for RC
5 Should be "ti,dra7-pcie-ep" for EP
6 - phys : list of PHY specifiers (used by generic PHY framework)
7 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
9 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
10 where <X> is the instance number of the pcie from the HW spec.
11 - num-lanes as specified in ../designware-pcie.txt
15 - reg : Two register ranges as listed in the reg-names property
16 - reg-names : The first entry must be "ti-conf" for the TI-specific registers
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| /kernel/linux/linux-5.10/drivers/phy/samsung/ |
| D | phy-exynos-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung Exynos SoC series PCIe PHY driver
5 * Phy provider for PCIe controller on Exynos SoC series
23 /* PCIe Purple registers */
32 /* PCIe PHY registers */
66 /* For Exynos pcie phy */
86 struct exynos_pcie_phy *ep = phy_get_drvdata(phy); in exynos5440_pcie_phy_init() local
89 exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK); in exynos5440_pcie_phy_init()
92 exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE); in exynos5440_pcie_phy_init()
95 exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0); in exynos5440_pcie_phy_init()
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| /kernel/linux/linux-4.19/drivers/phy/samsung/ |
| D | phy-exynos-pcie.c | 2 * Samsung EXYNOS SoC series PCIe PHY driver
4 * Phy provider for PCIe controller on Exynos SoC series
26 /* PCIe Purple registers */
35 /* PCIe PHY registers */
69 /* For Exynos pcie phy */
89 struct exynos_pcie_phy *ep = phy_get_drvdata(phy); in exynos5440_pcie_phy_init() local
92 exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK); in exynos5440_pcie_phy_init()
95 exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE); in exynos5440_pcie_phy_init()
98 exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0); in exynos5440_pcie_phy_init()
99 exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1); in exynos5440_pcie_phy_init()
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