| /kernel/linux/linux-4.19/drivers/pci/controller/ |
| D | pcie-cadence.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
8 #include "pcie-cadence.h"
10 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 fn, in cdns_pcie_set_outbound_region() argument
18 u64 sz = 1ULL << fls64(size - 1); in cdns_pcie_set_outbound_region()
30 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), addr0); in cdns_pcie_set_outbound_region()
31 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), addr1); in cdns_pcie_set_outbound_region()
33 /* Set the PCIe header descriptor */ in cdns_pcie_set_outbound_region()
42 * PCIe descriptor, the PCI function number must be set into in cdns_pcie_set_outbound_region()
[all …]
|
| D | pcie-iproc-platform.c | 1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/phy/phy.h>
20 #include "pcie-iproc.h"
24 .compatible = "brcm,iproc-pcie",
27 .compatible = "brcm,iproc-pcie-paxb-v2",
30 .compatible = "brcm,iproc-pcie-paxc",
33 .compatible = "brcm,iproc-pcie-paxc-v2",
42 struct device *dev = &pdev->dev; in iproc_pcie_pltfm_probe()
43 struct iproc_pcie *pcie; in iproc_pcie_pltfm_probe() local
44 struct device_node *np = dev->of_node; in iproc_pcie_pltfm_probe()
[all …]
|
| /kernel/linux/linux-5.10/drivers/pci/controller/cadence/ |
| D | pcie-cadence.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
8 #include "pcie-cadence.h"
10 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) in cdns_pcie_detect_quiet_min_delay_set() argument
18 ltssm_control_cap = cdns_pcie_readl(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP); in cdns_pcie_detect_quiet_min_delay_set()
23 cdns_pcie_writel(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP, ltssm_control_cap); in cdns_pcie_detect_quiet_min_delay_set()
26 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, in cdns_pcie_set_outbound_region() argument
34 u64 sz = 1ULL << fls64(size - 1); in cdns_pcie_set_outbound_region()
46 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), addr0); in cdns_pcie_set_outbound_region()
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/phy/ |
| D | brcm,cygnus-pcie-phy.txt | 1 Broadcom Cygnus PCIe PHY
4 - compatible: must be "brcm,cygnus-pcie-phy"
5 - reg: base address and length of the PCIe PHY block
6 - #address-cells: must be 1
7 - #size-cells: must be 0
9 Each PCIe PHY should be represented by a child node
12 - reg: the PHY ID
13 0 - PCIe RC 0
14 1 - PCIe RC 1
15 - #phy-cells: must be 0
[all …]
|
| D | nvidia,tegra124-xusb-padctl.txt | 11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
15 ports (e.g. PCIe) and the lanes.
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
[all …]
|
| D | qcom-qmp-phy.txt | 1 Qualcomm QMP PHY controller
4 QMP phy controller supports physical layer functionality for a number of
5 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
8 - compatible: compatible list, contains:
9 "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
10 "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
11 "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
12 "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
13 "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845.
15 - reg:
[all …]
|
| D | brcm,sr-pcie-phy.txt | 1 Broadcom Stingray PCIe PHY
4 - compatible: must be "brcm,sr-pcie-phy"
5 - reg: base address and length of the PCIe SS register space
6 - brcm,sr-cdru: phandle to the CDRU syscon node
7 - brcm,sr-mhb: phandle to the MHB syscon node
8 - #phy-cells: Must be 1, denotes the PHY index
11 PHY index goes from 0 to 7
13 For the internal PAXC based root complex, PHY index is always 8
17 compatible = "brcm,sr-mhb", "syscon";
22 compatible = "brcm,sr-cdru", "syscon";
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | brcm,cygnus-pcie-phy.txt | 1 Broadcom Cygnus PCIe PHY
4 - compatible: must be "brcm,cygnus-pcie-phy"
5 - reg: base address and length of the PCIe PHY block
6 - #address-cells: must be 1
7 - #size-cells: must be 0
9 Each PCIe PHY should be represented by a child node
12 - reg: the PHY ID
13 0 - PCIe RC 0
14 1 - PCIe RC 1
15 - #phy-cells: must be 0
[all …]
|
| D | nvidia,tegra124-xusb-padctl.txt | 11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
15 ports (e.g. PCIe) and the lanes.
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
[all …]
|
| D | lantiq,vrx200-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13 "#phy-cells":
15 description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
19 - lantiq,vrx200-pcie-phy
20 - lantiq,arx300-pcie-phy
[all …]
|
| D | qcom,qmp-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP PHY controller
11 - Manu Gautam <mgautam@codeaurora.org>
14 QMP phy controller supports physical layer functionality for a number of
15 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
20 - qcom,ipq8074-qmp-pcie-phy
21 - qcom,ipq8074-qmp-usb3-phy
[all …]
|
| D | brcm,sr-pcie-phy.txt | 1 Broadcom Stingray PCIe PHY
4 - compatible: must be "brcm,sr-pcie-phy"
5 - reg: base address and length of the PCIe SS register space
6 - brcm,sr-cdru: phandle to the CDRU syscon node
7 - brcm,sr-mhb: phandle to the MHB syscon node
8 - #phy-cells: Must be 1, denotes the PHY index
11 PHY index goes from 0 to 7
13 For the internal PAXC based root complex, PHY index is always 8
17 compatible = "brcm,sr-mhb", "syscon";
22 compatible = "brcm,sr-cdru", "syscon";
[all …]
|
| /kernel/linux/linux-5.10/drivers/pci/controller/dwc/ |
| D | pcie-armada8k.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Marvell Armada-8K SoCs
5 * Armada-8K PCIe Glue Layer Source Code
20 #include <linux/phy/phy.h>
26 #include "pcie-designware.h"
34 struct phy *phy[ARMADA8K_PCIE_MAX_LANES]; member
62 * AR/AW Cache defaults: Normal memory, Write-Back, Read / Write
72 #define to_armada8k_pcie(x) dev_get_drvdata((x)->dev)
74 static void armada8k_pcie_disable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_disable_phys() argument
79 phy_power_off(pcie->phy[i]); in armada8k_pcie_disable_phys()
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/pci/ |
| D | rockchip-pcie-host.txt | 1 * Rockchip AXI PCIe Root Port Bridge DT description
4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
[all …]
|
| D | samsung,exynos5440-pcie.txt | 1 * Samsung Exynos 5440 PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
7 - compatible: "samsung,exynos5440-pcie"
8 - reg: base addresses and lengths of the PCIe controller,
9 - reg-names : First name should be set to "elbi".
12 NOTE: When using the "config" property, reg-names must be set.
13 - interrupts: A list of interrupt outputs for level interrupt,
15 - phys: From PHY binding. Phandle for the generic PHY.
16 Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
[all …]
|
| D | rockchip-pcie-ep.txt | 1 * Rockchip AXI PCIe Endpoint Controller DT description
4 - compatible: Should contain "rockchip,rk3399-pcie-ep"
5 - reg: Two register ranges as listed in the reg-names property
6 - reg-names: Must include the following names
7 - "apb-base"
8 - "mem-base"
9 - clocks: Must contain an entry for each entry in clock-names.
10 See ../clocks/clock-bindings.txt for details.
11 - clock-names: Must include the following entries:
12 - "aclk"
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | rockchip-pcie-host.txt | 1 * Rockchip AXI PCIe Root Port Bridge DT description
4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
[all …]
|
| D | pci-keystone.txt | 1 TI Keystone PCIe interface
4 hardware version 3.65. It shares common functions with the PCIe DesignWare
6 Documentation/devicetree/bindings/pci/designware-pcie.txt
8 Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
12 Required Properties:-
14 compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
15 Should be "ti,am654-pcie-rc" for RC on AM654x SoC
16 reg: Three register ranges as listed in the reg-names property
17 reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
22 interrupt-cells: should be set to 1
[all …]
|
| D | samsung,exynos5440-pcie.txt | 1 * Samsung Exynos 5440 PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
7 - compatible: "samsung,exynos5440-pcie"
8 - reg: base addresses and lengths of the PCIe controller,
9 - reg-names : First name should be set to "elbi".
12 NOTE: When using the "config" property, reg-names must be set.
13 - interrupts: A list of interrupt outputs for level interrupt,
15 - phys: From PHY binding. Phandle for the generic PHY.
16 Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
[all …]
|
| D | rockchip-pcie-ep.txt | 1 * Rockchip AXI PCIe Endpoint Controller DT description
4 - compatible: Should contain "rockchip,rk3399-pcie-ep"
5 - reg: Two register ranges as listed in the reg-names property
6 - reg-names: Must include the following names
7 - "apb-base"
8 - "mem-base"
9 - clocks: Must contain an entry for each entry in clock-names.
10 See ../clocks/clock-bindings.txt for details.
11 - clock-names: Must include the following entries:
12 - "aclk"
[all …]
|
| /kernel/linux/linux-4.19/drivers/phy/broadcom/ |
| D | phy-bcm-sr-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Broadcom
12 #include <linux/phy/phy.h>
18 #define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
40 * struct sr_pcie_phy - Stingray PCIe PHY
42 * @core: pointer to the Stingray PCIe PHY core control
43 * @index: PHY index
44 * @phy: pointer to the kernel PHY device
49 struct phy *phy; member
53 * struct sr_pcie_phy_core - Stingray PCIe PHY core control
[all …]
|
| D | phy-bcm-cygnus-pcie.c | 18 #include <linux/phy/phy.h>
34 * struct cygnus_pcie_phy - Cygnus PCIe PHY device
35 * @core: pointer to the Cygnus PCIe PHY core control
36 * @id: internal ID to identify the Cygnus PCIe PHY
37 * @phy: pointer to the kernel PHY device
42 struct phy *phy; member
46 * struct cygnus_pcie_phy_core - Cygnus PCIe PHY core control
50 * @phys: pointer to Cygnus PHY device
59 static int cygnus_pcie_power_config(struct cygnus_pcie_phy *phy, bool enable) in cygnus_pcie_power_config() argument
61 struct cygnus_pcie_phy_core *core = phy->core; in cygnus_pcie_power_config()
[all …]
|
| /kernel/linux/linux-5.10/drivers/phy/broadcom/ |
| D | phy-bcm-sr-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Broadcom
12 #include <linux/phy/phy.h>
18 #define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
40 * struct sr_pcie_phy - Stingray PCIe PHY
42 * @core: pointer to the Stingray PCIe PHY core control
43 * @index: PHY index
44 * @phy: pointer to the kernel PHY device
49 struct phy *phy; member
53 * struct sr_pcie_phy_core - Stingray PCIe PHY core control
[all …]
|
| D | phy-bcm-cygnus-pcie.c | 18 #include <linux/phy/phy.h>
34 * struct cygnus_pcie_phy - Cygnus PCIe PHY device
35 * @core: pointer to the Cygnus PCIe PHY core control
36 * @id: internal ID to identify the Cygnus PCIe PHY
37 * @phy: pointer to the kernel PHY device
42 struct phy *phy; member
46 * struct cygnus_pcie_phy_core - Cygnus PCIe PHY core control
50 * @phys: pointer to Cygnus PHY device
59 static int cygnus_pcie_power_config(struct cygnus_pcie_phy *phy, bool enable) in cygnus_pcie_power_config() argument
61 struct cygnus_pcie_phy_core *core = phy->core; in cygnus_pcie_power_config()
[all …]
|
| /kernel/linux/linux-5.10/drivers/pci/controller/ |
| D | pcie-iproc-platform.c | 1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/phy/phy.h>
20 #include "pcie-iproc.h"
24 .compatible = "brcm,iproc-pcie",
27 .compatible = "brcm,iproc-pcie-paxb-v2",
30 .compatible = "brcm,iproc-pcie-paxc",
33 .compatible = "brcm,iproc-pcie-paxc-v2",
42 struct device *dev = &pdev->dev; in iproc_pcie_pltfm_probe()
43 struct iproc_pcie *pcie; in iproc_pcie_pltfm_probe() local
44 struct device_node *np = dev->of_node; in iproc_pcie_pltfm_probe()
[all …]
|