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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/
Dsifive,plic-1.0.0.txt1 SiFive Platform-Level Interrupt Controller (PLIC)
2 -------------------------------------------------
4 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
5 (PLIC) high-level specification in the RISC-V Privileged Architecture
7 hart contexts in the system, via the external interrupt source in each hart.
9 A hart context is a privilege mode in a hardware execution thread. For example,
10 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
11 privilege modes per hart; machine mode and supervisor mode.
13 Each interrupt can be enabled on per-context basis. Any context can claim
21 While the PLIC supports both edge-triggered and level-triggered interrupts,
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
12 (PLIC) high-level specification in the RISC-V Privileged Architecture
14 hart contexts in the system, via the external interrupt source in each hart.
16 A hart context is a privilege mode in a hardware execution thread. For example,
17 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
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/kernel/linux/linux-4.19/drivers/clocksource/
Driscv_timer.c1 // SPDX-License-Identifier: GPL-2.0
14 * All RISC-V systems have a timer attached to every hart. These timers can be
16 * events. In order to abstract the architecture-specific timer reading and
21 * As the timers are inherently a per-cpu resource, these callbacks perform
22 * operations on the current hart. There is guaranteed to be exactly one timer
23 * per hart on all RISC-V systems.
63 ce->cpumask = cpumask_of(cpu); in riscv_timer_starting_cpu()
76 /* called directly from the low-level interrupt handler */
82 evdev->event_handler(evdev); in riscv_timer_interrupt()
DKconfig142 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
165 32-bit free running decrementing counters.
225 bool "Integrator-ap timer driver" if COMPILE_TEST
228 Enables support for the Integrator-ap timer.
268 available on many OMAP-like platforms.
293 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
297 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
302 bool "Support for 64-bit counters in ARC HS38 cores" if COMPILE_TEST
306 This enables 2 different 64-bit timers: RTC (for UP) and GFRC (for SMP)
324 power-of-2 divisor of the clock rate. The behaviour can also be
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/kernel/linux/linux-5.10/drivers/irqchip/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
216 bool "J-Core integrated AIC" if COMPILE_TEST
220 Support for the J-Core integrated AIC.
231 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
234 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
239 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
274 tristate "TS-4800 IRQ controller"
279 Support for the TS-4800 FPGA IRQ controller
443 bool "C-SKY Multi Processor Interrupt Controller"
446 Say yes here to enable C-SKY SMP interrupt controller driver used
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/
Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iio/temperature/
Dadi,ltc2983.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices LTC2983 Multi-sensor Temperature system
10 - Nuno Sá <nuno.sa@analog.com>
13 Analog Devices LTC2983 Multi-Sensor Digital Temperature Measurement System
14 https://www.analog.com/media/en/technical-documentation/data-sheets/2983fc.pdf
19 - adi,ltc2983
27 adi,mux-delay-config-us:
29 The LTC2983 performs 2 or 3 internal conversion cycles per temperature
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/kernel/linux/linux-4.19/Documentation/timers/
Dhighres.txt2 -----------------------------------------------------
7 https://www.kernel.org/doc/ols/2006/ols2006v1-pages-333-346.pdf
10 http://www.cs.columbia.edu/~nahum/w6998/papers/ols2006-hrtimers-slides.pdf
22 - hrtimer base infrastructure
23 - timeofday and clock source management
24 - clock event management
25 - high resolution timer functionality
26 - dynamic ticks
30 ---------------------------
38 - time ordered enqueueing into a rb-tree
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/kernel/linux/linux-5.10/Documentation/timers/
Dhighres.rst8 https://www.kernel.org/doc/ols/2006/ols2006v1-pages-333-346.pdf
11 http://www.cs.columbia.edu/~nahum/w6998/papers/ols2006-hrtimers-slides.pdf
23 - hrtimer base infrastructure
24 - timeofday and clock source management
25 - clock event management
26 - high resolution timer functionality
27 - dynamic ticks
31 ---------------------------
40 - time ordered enqueueing into a rb-tree
41 - independent of ticks (the processing is based on nanoseconds)
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/kernel/liteos_m/arch/risc-v/nuclei/gcc/nmsis/Core/Include/
Dcore_feature_pmp.h4 * SPDX-License-Identifier: Apache-2.0
10 * www.apache.org/licenses/LICENSE-2.0
42 * Optional physical memory protection (PMP) unit provides per-hart machine-mode
58 * \param [in] idx PMP region index(0-15)
70 idx -= 4; in __get_PMPxCFG()
73 idx -= 8; in __get_PMPxCFG()
76 idx -= 12; in __get_PMPxCFG()
86 idx -= 8; in __get_PMPxCFG()
100 * \param [in] idx PMPx region index(0-15)
115 idx -= 4; in __set_PMPxCFG()
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/kernel/linux/linux-5.10/drivers/clocksource/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
164 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
187 32-bit free running decrementing counters.
241 bool "Integrator-AP timer driver" if COMPILE_TEST
244 Enables support for the Integrator-AP timer.
277 available on many OMAP-like platforms.
286 It has a 64-bit counter with update rate up to 1000MHz.
287 This counter is accessed via couple of 32-bit memory-mapped registers.
306 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
310 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
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/kernel/linux/linux-4.19/Documentation/RCU/
DRTFP.txt4 This document describes RCU-related publications, and is followed by
19 with short-lived threads, such as the K42 research operating system.
20 However, Linux has long-lived tasks, so more is needed.
23 serialization, which is an RCU-like mechanism that relies on the presence
27 that these overheads were not so expensive in the mid-80s. Nonetheless,
28 passive serialization appears to be the first deferred-destruction
30 has lapsed, so this approach may be used in non-GPL software, if desired.
34 In 1987, Rashid et al. described lazy TLB-flush [RichardRashid87a].
36 this paper helped inspire the update-side batching used in the later
38 a description of Argus that noted that use of out-of-date values can
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/kernel/linux/linux-5.10/Documentation/RCU/
DRTFP.txt4 This document describes RCU-related publications, and is followed by
19 with short-lived threads, such as the K42 research operating system.
20 However, Linux has long-lived tasks, so more is needed.
23 serialization, which is an RCU-like mechanism that relies on the presence
27 that these overheads were not so expensive in the mid-80s. Nonetheless,
28 passive serialization appears to be the first deferred-destruction
30 has lapsed, so this approach may be used in non-GPL software, if desired.
34 In 1987, Rashid et al. described lazy TLB-flush [RichardRashid87a].
36 this paper helped inspire the update-side batching used in the later
38 a description of Argus that noted that use of out-of-date values can
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/kernel/linux/linux-5.10/drivers/platform/x86/
Dwmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ACPI-WMI mapping driver
5 * Copyright (C) 2007-2008 Carlos Corbacho <carlos@strangeworlds.co.uk>
9 * Copyright (c) 2001-2007 Anton Altaparmakov
12 * WMI bus infrastructure by Andrew Lutomirski and Darren Hart:
37 MODULE_DESCRIPTION("ACPI-WMI Mapping Driver");
101 .name = "acpi-wmi",
122 block = &wblock->gblock; in find_guid()
124 if (memcmp(block->guid, &guid_input, 16) == 0) { in find_guid()
141 if (wdriver->id_table == NULL) in find_guid_context()
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/kernel/linux/linux-4.19/drivers/platform/x86/
Dwmi.c2 * ACPI-WMI mapping driver
4 * Copyright (C) 2007-2008 Carlos Corbacho <carlos@strangeworlds.co.uk>
8 * Copyright (c) 2001-2007 Anton Altaparmakov
11 * WMI bus infrastructure by Andrew Lutomirski and Darren Hart:
29 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
53 MODULE_DESCRIPTION("ACPI-WMI Mapping Driver");
117 .name = "acpi-wmi",
138 block = &wblock->gblock; in find_guid()
140 if (memcmp(block->guid, &guid_input, 16) == 0) { in find_guid()
158 return -ENOENT; in get_subobj_info()
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/kernel/linux/linux-4.19/kernel/
Dfutex.c15 * PI-futex support started by Ingo Molnar and Thomas Gleixner
22 * Requeue-PI support by Darren Hart <dvhltc@us.ibm.com>
28 * Kirkwood for proof-of-concept implementation.
45 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
70 #include <linux/fault-inject.h>
130 * smp_mb(); (A) <-- paired with -.
139 * `--------> smp_mb(); (B)
146 * waiters--; (b) unlock(hash_bucket(futex));
150 * to futex and the waiters read -- this is done by the barriers for both
171 * acquiring the lock. It then decrements them again after releasing it -
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/kernel/linux/linux-5.10/kernel/
Dfutex.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 * PI-futex support started by Ingo Molnar and Thomas Gleixner
23 * Requeue-PI support by Darren Hart <dvhltc@us.ibm.com>
29 * Kirkwood for proof-of-concept implementation.
40 #include <linux/fault-inject.h>
101 * smp_mb(); (A) <-- paired with -.
110 * `--------> smp_mb(); (B)
117 * waiters--; (b) unlock(hash_bucket(futex));
141 * acquiring the lock. It then decrements them again after releasing it -
161 * NOMMU does not have per process address space. Let the compiler optimize
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/kernel/linux/linux-4.19/
DMAINTAINERS28 'diff -u' to make the patch easy to merge. Be prepared to get your
38 See Documentation/process/coding-style.rst for guidance here.
44 See Documentation/process/submitting-patches.rst for details.
55 include a Signed-off-by: line. The current version of this
57 Documentation/process/submitting-patches.rst.
68 that the bug would present a short-term risk to other users if it
84 W: Web-page with status/info
85 B: URI for where to file bugs. A web-page with detailed bug
107 One pattern per line. Multiple F: lines acceptable.
109 N: [^a-z]tegra all files whose path contains the word tegra
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/kernel/linux/linux-5.10/
DMAINTAINERS9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
97 W: *Web-page* with status/info
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