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14 …"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing P…21 …ued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issue…28 …NG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issue…42 …"PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the S…49 … issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issue…56 …he SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issue…70 …"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing t…77 …ued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issue…84 …EA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issue…98 …"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing t…[all …]
14 …counts the total number of CPU cycles when the ECC coprocessor is busy performing the elliptic-cur…21 … issued by the CPU and are blocked because the ECC coprocessor is busy performing a function issue…28 … (ECC) functions issued by the CPU because the ECC coprocessor is busy performing a function issue…
16 trap to SIGBUS any code performing unaligned access (good for debugging bad32 0 A user process performing an unaligned memory access38 performing the unaligned access. This is of course43 performing the unaligned access.
20 trap to SIGBUS any code performing unaligned access (good for debugging bad36 0 A user process performing an unaligned memory access42 performing the unaligned access. This is of course47 performing the unaligned access.
37 this relationship. The highest performing initiator to a given target105 slower performing memory cached by a smaller higher performing memory. The108 higher performing memory to transparently cache access to progressively112 hierarchy. Each increasing cache level provides higher performing118 performing. In contrast, the memory cache level is centric to the last
102 * Halting simply requires that the secondary CPUs stop performing any114 * Power-off simply requires that the secondary CPUs stop performing any129 * Restart requires that the secondary CPUs stop performing any activity
99 * Halting simply requires that the secondary CPUs stop performing any111 * Power-off simply requires that the secondary CPUs stop performing any126 * Restart requires that the secondary CPUs stop performing any activity
71 * against the value of the cpu_id field before performing a rseq85 * with the cpu_id_start value previously read, before performing
10 * that is called as part of performing resync/recovery/reshape.175 /* During a reshape we might be performing IO on the
54 * struct pci_epf_ops - set of function pointers for performing EPF operations73 * @ops: set of function pointers for performing EPF operations
153 when performing error recovery actions.174 If an error message indicates a non-fatal error, performing link reset188 a hierarchy in question. Then, performing link reset at upstream is
72 * On these Samsung MoviNAND parts, performing secure erase or94 * On Some Kingston eMMCs, performing trim can result in
60 * struct pci_epf_ops - set of function pointers for performing EPF operations76 * @ops: set of function pointers for performing EPF operations