| /kernel/linux/linux-5.10/drivers/clk/hisilicon/ |
| D | clk-hisi-phase.c | 5 * Simple HiSilicon phase clock implementation.
30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
48 regval = (regval & phase->mask) >> phase->shift; in hisi_clk_get_phase()
50 return hisi_phase_regval_to_degrees(phase, regval); in hisi_clk_get_phase()
53 static int hisi_phase_degrees_to_regval(struct clk_hisi_phase *phase, in hisi_phase_degrees_to_regval() argument
[all …]
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| /kernel/linux/linux-4.19/drivers/clk/hisilicon/ |
| D | clk-hisi-phase.c | 5 * Simple HiSilicon phase clock implementation.
30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
48 regval = (regval & phase->mask) >> phase->shift; in hisi_clk_get_phase()
50 return hisi_phase_regval_to_degrees(phase, regval); in hisi_clk_get_phase()
53 static int hisi_phase_degrees_to_regval(struct clk_hisi_phase *phase, in hisi_phase_degrees_to_regval() argument
[all …]
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| /kernel/linux/linux-4.19/drivers/clk/sunxi-ng/ |
| D | ccu_phase.c | 18 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
25 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
26 delay = (reg >> phase->shift); in ccu_phase_get_phase()
27 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
61 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_set_phase() local
113 spin_lock_irqsave(phase->common.lock, flags); in ccu_phase_set_phase()
114 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_set_phase()
115 reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift); in ccu_phase_set_phase()
116 writel(reg | (delay << phase->shift), in ccu_phase_set_phase()
117 phase->common.base + phase->common.reg); in ccu_phase_set_phase()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/sunxi-ng/ |
| D | ccu_phase.c | 15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
58 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_set_phase() local
110 spin_lock_irqsave(phase->common.lock, flags); in ccu_phase_set_phase()
111 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_set_phase()
112 reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift); in ccu_phase_set_phase()
113 writel(reg | (delay << phase->shift), in ccu_phase_set_phase()
114 phase->common.base + phase->common.reg); in ccu_phase_set_phase()
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| /kernel/linux/linux-5.10/Documentation/hwmon/ |
| D | max16601.rst | 64 curr2_input VCORE phase 0 input current.
67 curr3_input VCORE phase 1 input current.
70 curr4_input VCORE phase 2 input current.
73 curr5_input VCORE phase 3 input current.
76 curr6_input VCORE phase 4 input current.
79 curr7_input VCORE phase 5 input current.
82 curr8_input VCORE phase 6 input current.
85 curr9_input VCORE phase 7 input current.
101 curr13_input VCORE phase 0 output current.
104 curr14_input VCORE phase 1 output current.
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clock_source.h | 60 SRII(PHASE, DP_DTO, 0),\
61 SRII(PHASE, DP_DTO, 1),\
62 SRII(PHASE, DP_DTO, 2),\
63 SRII(PHASE, DP_DTO, 3),\
64 SRII(PHASE, DP_DTO, 4),\
65 SRII(PHASE, DP_DTO, 5),\
81 SRII(PHASE, DP_DTO, 0),\
82 SRII(PHASE, DP_DTO, 1),\
83 SRII(PHASE, DP_DTO, 2),\
84 SRII(PHASE, DP_DTO, 3),\
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| /kernel/linux/linux-5.10/drivers/clk/meson/ |
| D | clk-phase.c | 11 #include "clk-phase.h"
40 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_get_phase() local
43 val = meson_parm_read(clk->map, &phase->ph); in meson_clk_phase_get_phase()
45 return meson_clk_degrees_from_val(val, phase->ph.width); in meson_clk_phase_get_phase()
51 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_set_phase() local
54 val = meson_clk_degrees_to_val(degrees, phase->ph.width); in meson_clk_phase_set_phase()
55 meson_parm_write(clk->map, &phase->ph, val); in meson_clk_phase_set_phase()
68 * The phase of mst_sclk clock output can be controlled independently
72 * If necessary, we can still control the phase in the tdm block
87 /* Get phase 0 and sync it to phase 1 and 2 */ in meson_clk_triphase_sync()
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| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| D | sdhci-sirf.c | 77 int phase; in sdhci_sirf_execute_tuning() local
88 phase = 0; in sdhci_sirf_execute_tuning()
92 clock_setting | phase, in sdhci_sirf_execute_tuning()
98 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n", in sdhci_sirf_execute_tuning()
99 mmc_hostname(mmc), phase); in sdhci_sirf_execute_tuning()
101 start = phase; in sdhci_sirf_execute_tuning()
102 end = phase; in sdhci_sirf_execute_tuning()
104 if (phase == (SIRF_TUNING_COUNT - 1) in sdhci_sirf_execute_tuning()
108 dev_dbg(mmc_dev(mmc), "%s: Found bad phase = %d\n", in sdhci_sirf_execute_tuning()
109 mmc_hostname(mmc), phase); in sdhci_sirf_execute_tuning()
[all …]
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| /kernel/linux/linux-4.19/drivers/clk/sunxi/ |
| D | clk-mod0.c | 183 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_get_phase() local
189 value = readl(phase->reg); in mmc_get_phase()
190 delay = (value >> phase->offset) & 0x3; in mmc_get_phase()
225 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_set_phase() local
276 spin_lock_irqsave(phase->lock, flags); in mmc_set_phase()
277 value = readl(phase->reg); in mmc_set_phase()
278 value &= ~GENMASK(phase->offset + 3, phase->offset); in mmc_set_phase()
279 value |= delay << phase->offset; in mmc_set_phase()
280 writel(value, phase->reg); in mmc_set_phase()
281 spin_unlock_irqrestore(phase->lock, flags); in mmc_set_phase()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/sunxi/ |
| D | clk-mod0.c | 175 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_get_phase() local
181 value = readl(phase->reg); in mmc_get_phase()
182 delay = (value >> phase->offset) & 0x3; in mmc_get_phase()
217 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_set_phase() local
268 spin_lock_irqsave(phase->lock, flags); in mmc_set_phase()
269 value = readl(phase->reg); in mmc_set_phase()
270 value &= ~GENMASK(phase->offset + 3, phase->offset); in mmc_set_phase()
271 value |= delay << phase->offset; in mmc_set_phase()
272 writel(value, phase->reg); in mmc_set_phase()
273 spin_unlock_irqrestore(phase->lock, flags); in mmc_set_phase()
[all …]
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| /kernel/linux/linux-5.10/drivers/hwmon/pmbus/ |
| D | mp2975.c | 3 * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers
90 mp2975_read_word_helper(struct i2c_client *client, int page, int phase, u8 reg, in mp2975_read_word_helper() argument
93 int ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_word_helper()
122 int page, int phase, u8 reg) in mp2975_read_phase() argument
126 ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_phase()
130 if (!((phase + 1) % MP2975_PAGE_NUM)) in mp2975_read_phase()
141 * - Rcs is the internal phase current sense resistor which is constant in mp2975_read_phase()
147 * Current phase sensing, providing by the device is not accurate in mp2975_read_phase()
150 * case phase current is represented as the maximum between the value in mp2975_read_phase()
153 ret = pmbus_read_word_data(client, page, phase, PMBUS_READ_IOUT); in mp2975_read_phase()
[all …]
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| D | ir35221.c | 25 int phase, int reg) in ir35221_read_word_data() argument
31 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
35 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
39 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
43 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
47 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
51 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
55 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
59 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
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| /kernel/linux/linux-4.19/drivers/mmc/host/ |
| D | sdhci-sirf.c | 83 int phase; in sdhci_sirf_execute_tuning() local
94 phase = 0; in sdhci_sirf_execute_tuning()
98 clock_setting | phase, in sdhci_sirf_execute_tuning()
104 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n", in sdhci_sirf_execute_tuning()
105 mmc_hostname(mmc), phase); in sdhci_sirf_execute_tuning()
107 start = phase; in sdhci_sirf_execute_tuning()
108 end = phase; in sdhci_sirf_execute_tuning()
110 if (phase == (SIRF_TUNING_COUNT - 1) in sdhci_sirf_execute_tuning()
114 dev_dbg(mmc_dev(mmc), "%s: Found bad phase = %d\n", in sdhci_sirf_execute_tuning()
115 mmc_hostname(mmc), phase); in sdhci_sirf_execute_tuning()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/tidss/ |
| D | tidss_dispc_regs.h | 120 #define DISPC_VID_FIR_COEF_H0(phase) (0x6c + (phase) * 4) argument
122 #define DISPC_VID_FIR_COEF_H0_C(phase) (0x90 + (phase) * 4) argument
125 #define DISPC_VID_FIR_COEF_H12(phase) (0xb4 + (phase) * 4) argument
127 #define DISPC_VID_FIR_COEF_H12_C(phase) (0xf4 + (phase) * 4) argument
130 #define DISPC_VID_FIR_COEF_V0(phase) (0x134 + (phase) * 4) argument
132 #define DISPC_VID_FIR_COEF_V0_C(phase) (0x158 + (phase) * 4) argument
135 #define DISPC_VID_FIR_COEF_V12(phase) (0x17c + (phase) * 4) argument
137 #define DISPC_VID_FIR_COEF_V12_C(phase) (0x1bc + (phase) * 4) argument
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| /kernel/linux/linux-5.10/drivers/gpu/drm/imx/dcss/ |
| D | dcss-scaler.c | 176 int phase; in dcss_scaler_gaussian_filter() local
181 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
182 coef[phase][0] = 0; in dcss_scaler_gaussian_filter()
183 coef[phase][PSC_NUM_TAPS - 1] = 0; in dcss_scaler_gaussian_filter()
223 /* override phase 0 with identity filter if specified */ in dcss_scaler_gaussian_filter()
230 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
235 sum += coef[phase][i]; in dcss_scaler_gaussian_filter()
237 ll_temp = coef[phase][i]; in dcss_scaler_gaussian_filter()
241 coef[phase][i] = (int)ll_temp; in dcss_scaler_gaussian_filter()
251 * @use_5_taps: 0 for 7 taps per phase, 1 for 5 taps
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | exynos-dw-mshc.txt | 30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
31 in transmit mode and CIU clock phase shift value in receive mode for single
35 * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
36 in transmit mode and CIU clock phase shift value in receive mode for double
39 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
45 - First Cell: CIU clock phase shift value for tx mode.
46 - Second Cell: CIU clock phase shift value for rx mode.
49 - valid value for tx phase shift and rx phase shift is 0 to 7.
50 - when CIU clock divider value is set to 3, all possible 8 phase shift
53 phase shift clocks should be 0.
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mmc/ |
| D | exynos-dw-mshc.txt | 30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
31 in transmit mode and CIU clock phase shift value in receive mode for single
35 * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
36 in transmit mode and CIU clock phase shift value in receive mode for double
39 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
45 - First Cell: CIU clock phase shift value for tx mode.
46 - Second Cell: CIU clock phase shift value for rx mode.
49 - valid value for tx phase shift and rx phase shift is 0 to 7.
50 - when CIU clock divider value is set to 3, all possible 8 phase shift
53 phase shift clocks should be 0.
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| /kernel/linux/linux-4.19/drivers/char/ |
| D | ppdev.c | 24 * SETPHASE set the IEEE 1284 phase of a particular mode. Not to be
41 * GETPHASE gets the current IEEE1284 phase
396 pp->saved_state.phase = info->phase; in pp_do_ioctl()
398 info->phase = pp->state.phase; in pp_do_ioctl()
427 pp->state.phase = init_phase(mode); in pp_do_ioctl()
431 pp->pdev->port->ieee1284.phase = pp->state.phase; in pp_do_ioctl()
451 int phase; in pp_do_ioctl() local
453 if (copy_from_user(&phase, argp, sizeof(phase))) in pp_do_ioctl()
456 /* FIXME: validate phase */ in pp_do_ioctl()
457 pp->state.phase = phase; in pp_do_ioctl()
[all …]
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| /kernel/linux/linux-5.10/drivers/char/ |
| D | ppdev.c | 20 * SETPHASE set the IEEE 1284 phase of a particular mode. Not to be
37 * GETPHASE gets the current IEEE1284 phase
397 pp->saved_state.phase = info->phase; in pp_do_ioctl()
399 info->phase = pp->state.phase; in pp_do_ioctl()
428 pp->state.phase = init_phase(mode); in pp_do_ioctl()
432 pp->pdev->port->ieee1284.phase = pp->state.phase; in pp_do_ioctl()
452 int phase; in pp_do_ioctl() local
454 if (copy_from_user(&phase, argp, sizeof(phase))) in pp_do_ioctl()
457 /* FIXME: validate phase */ in pp_do_ioctl()
458 pp->state.phase = phase; in pp_do_ioctl()
[all …]
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| /kernel/linux/linux-4.19/drivers/media/i2c/ |
| D | saa711x_regs.h | 112 /* Horizontal phase scaling */
159 /* Horizontal phase scaling */
422 /* Task A: Horizontal phase scaling */
426 "Task A: Horizontal luminance phase offset"},
431 "Task A: Horizontal chrominance phase offset"},
443 "Task A: Vertical chrominance phase offset '00'"},
445 "Task A: Vertical chrominance phase offset '01'"},
447 "Task A: Vertical chrominance phase offset '10'"},
449 "Task A: Vertical chrominance phase offset '11'"},
451 "Task A: Vertical luminance phase offset '00'"},
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| /kernel/linux/linux-5.10/drivers/media/i2c/ |
| D | saa711x_regs.h | 112 /* Horizontal phase scaling */
159 /* Horizontal phase scaling */
422 /* Task A: Horizontal phase scaling */
426 "Task A: Horizontal luminance phase offset"},
431 "Task A: Horizontal chrominance phase offset"},
443 "Task A: Vertical chrominance phase offset '00'"},
445 "Task A: Vertical chrominance phase offset '01'"},
447 "Task A: Vertical chrominance phase offset '10'"},
449 "Task A: Vertical chrominance phase offset '11'"},
451 "Task A: Vertical luminance phase offset '00'"},
[all …]
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| /kernel/linux/linux-5.10/include/trace/events/ |
| D | clk.h | 156 TP_PROTO(struct clk_core *core, int phase),
158 TP_ARGS(core, phase),
162 __field( int, phase )
167 __entry->phase = phase;
170 TP_printk("%s %d", __get_str(name), (int)__entry->phase)
175 TP_PROTO(struct clk_core *core, int phase),
177 TP_ARGS(core, phase)
182 TP_PROTO(struct clk_core *core, int phase),
184 TP_ARGS(core, phase)
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| /kernel/linux/linux-5.10/drivers/staging/iio/Documentation/ |
| D | sysfs-bus-iio-dds | 36 Stores phase into Y.
38 allows for pin controlled PSK Phase Shift Keying
40 control the desired phase Y which is added to the phase
48 the desired value in rad. If shared across all phase registers
56 Specifies the active phase Y which is added to the phase
68 phase is controlled by the respective phase and frequency
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| /kernel/linux/linux-4.19/drivers/staging/iio/Documentation/ |
| D | sysfs-bus-iio-dds | 36 Stores phase into Y.
38 allows for pin controlled PSK Phase Shift Keying
40 control the desired phase Y which is added to the phase
48 the desired value in rad. If shared across all phase registers
56 Specifies the active phase Y which is added to the phase
68 phase is controlled by the respective phase and frequency
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| /kernel/linux/linux-4.19/drivers/scsi/ |
| D | NCR5380.c | 74 * phase goes through the various phases as instructed by the target.
239 {BASR_PHASE_MATCH, "PHASE MATCH"},
319 * NCR5380_print_phase - show SCSI phase
322 * Print the current SCSI phase for debugging purposes
333 shost_printk(KERN_DEBUG, instance, "REQ not asserted, phase unknown.\n"); in NCR5380_print_phase()
338 shost_printk(KERN_DEBUG, instance, "phase %s\n", phases[i].name); in NCR5380_print_phase()
443 * the SCSI bus busy. Check for BUS FREE phase. If not, try to abort the
728 * Called by the interrupt handler when DMA finishes or a phase
742 p = hostdata->connected->SCp.phase; in NCR5380_dma_complete()
766 pr_err("scsi%d: bus stuck in data phase -- probably a single byte overrun!\n", in NCR5380_dma_complete()
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