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/kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/
Darmada-3720-turris-mox.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/bus/moxtet.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include "armada-372x.dtsi"
16 compatible = "cznic,turris-mox", "marvell,armada3720",
27 stdout-path = "serial0:115200n8";
36 compatible = "gpio-leds";
40 linux,default-trigger = "default-on";
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/
Dt1040rdb.dts4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t104xsi-pre.dtsi"
49 fixed-link = <0 1 1000 0 0>;
50 phy-connection-type = "sgmii";
54 fixed-link = <1 1 1000 0 0>;
55 phy-connection-type = "sgmii";
59 phy-handle = <&phy_sgmii_2>;
60 phy-connection-type = "sgmii";
64 phy_sgmii_2: ethernet-phy@3 {
68 /* VSC8514 QSGMII PHY */
[all …]
Dt4240rdb.dts4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
67 bank-width = <2>;
68 device-width = <1>;
[all …]
Dt2080qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
66 phy-handle = <&phy_sgmii_s3_1e>;
67 phy-connection-type = "xgmii";
71 phy-handle = <&phy_sgmii_s3_1f>;
72 phy-connection-type = "xgmii";
76 phy-handle = <&rgmii_phy1>;
[all …]
Dsbc8641d.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
12 /include/ "mpc8641si-pre.dtsi"
35 compatible = "cfi-flash";
37 bank-width = <2>;
38 device-width = <2>;
39 #address-cells = <1>;
40 #size-cells = <1>;
44 read-only;
49 read-only;
58 read-only;
[all …]
Dt4240qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "cfi-flash";
94 bank-width = <2>;
95 device-width = <1>;
[all …]
Dt2081qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
58 phy-handle = <&phy_sgmii_s7_1c>;
59 phy-connection-type = "sgmii";
63 phy-handle = <&phy_sgmii_s7_1d>;
64 phy-connection-type = "sgmii";
68 phy-handle = <&rgmii_phy1>;
[all …]
Dt2080rdb.dts2 * T2080PCIe-RDB Board Device Tree Source
4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
60 phy-handle = <&xg_aq1202_phy3>;
61 phy-connection-type = "xgmii";
65 phy-handle = <&xg_aq1202_phy4>;
66 phy-connection-type = "xgmii";
[all …]
Dt1042d4rdb.dts35 /include/ "t104xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
47 compatible = "fsl,t1040d4rdb-cpld",
48 "fsl,deepsleep-cpld";
55 phy-handle = <&phy_sgmii_0>;
56 phy-connection-type = "sgmii";
60 phy-handle = <&phy_sgmii_1>;
61 phy-connection-type = "sgmii";
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/mscc/
Docelot_pcb120.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/phy/phy-ocelot-serdes.h>
12 compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
15 stdout-path = "serial0:115200n8";
42 pinctrl-names = "default";
43 pinctrl-0 = <&miim1>, <&phy_int_pins>, <&phy_load_save_pins>;
45 phy7: ethernet-phy@0 {
[all …]
/kernel/linux/linux-4.19/arch/powerpc/boot/dts/fsl/
Dt4240rdb.dts4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
67 bank-width = <2>;
68 device-width = <1>;
[all …]
Dt2080qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
66 phy-handle = <&phy_sgmii_s3_1e>;
67 phy-connection-type = "xgmii";
71 phy-handle = <&phy_sgmii_s3_1f>;
72 phy-connection-type = "xgmii";
76 phy-handle = <&rgmii_phy1>;
[all …]
Dt4240qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "cfi-flash";
94 bank-width = <2>;
95 device-width = <1>;
[all …]
Dsbc8641d.dts16 /include/ "mpc8641si-pre.dtsi"
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <2>;
43 #address-cells = <1>;
44 #size-cells = <1>;
48 read-only;
53 read-only;
62 read-only;
67 compatible = "wrs,epld-localbus";
[all …]
Dt2081qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
58 phy-handle = <&phy_sgmii_s7_1c>;
59 phy-connection-type = "sgmii";
63 phy-handle = <&phy_sgmii_s7_1d>;
64 phy-connection-type = "sgmii";
68 phy-handle = <&rgmii_phy1>;
[all …]
Dt2080rdb.dts2 * T2080PCIe-RDB Board Device Tree Source
4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
60 phy-handle = <&xg_aq1202_phy3>;
61 phy-connection-type = "xgmii";
65 phy-handle = <&xg_aq1202_phy4>;
66 phy-connection-type = "xgmii";
[all …]
Dp4080ds.dts4 * Copyright 2009 - 2015 Freescale Semiconductor Inc.
35 /include/ "p4080si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 reserved-memory {
63 #address-cells = <2>;
64 #size-cells = <2>;
67 bman_fbpr: bman-fbpr {
71 qman_fqd: qman-fqd {
[all …]
Dt1042d4rdb.dts35 /include/ "t104xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
47 compatible = "fsl,t1040d4rdb-cpld",
48 "fsl,deepsleep-cpld";
55 phy-handle = <&phy_sgmii_0>;
56 phy-connection-type = "sgmii";
60 phy-handle = <&phy_sgmii_1>;
61 phy-connection-type = "sgmii";
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/freescale/
Dfsl-ls1043a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
10 /dts-v1/;
11 #include "fsl-ls1043a.dtsi"
25 stdout-path = "serial0:115200n8";
34 shunt-resistor = <1000>;
56 #address-cells = <2>;
57 #size-cells = <1>;
64 compatible = "cfi-flash";
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/
Dhisilicon-hip04-net.txt6 - compatible: should be "hisilicon,hip04-mac".
7 - reg: address and length of the register set for the device.
8 - interrupts: interrupt for the device.
9 - port-handle: <phandle port channel>
13 - phy-mode: see ethernet.txt [1].
16 - phy-handle: see ethernet.txt [1].
27 - compatible: "hisilicon,hip04-ppe", "syscon".
28 - reg: address and length of the register set for the device.
35 - compatible: should be "hisilicon,mdio".
36 - Inherits from MDIO bus node binding [2]
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dhisilicon-hip04-net.txt6 - compatible: should be "hisilicon,hip04-mac".
7 - reg: address and length of the register set for the device.
8 - interrupts: interrupt for the device.
9 - port-handle: <phandle port channel>
14 - phy-mode: see ethernet.txt [1].
17 - phy-handle: see ethernet.txt [1].
28 - compatible: "hisilicon,hip04-ppe", "syscon".
29 - reg: address and length of the register set for the device.
36 - compatible: should be "hisilicon,mdio".
37 - Inherits from MDIO bus node binding [2]
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dfsl-ls1043a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
16 compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
26 stdout-path = "serial0:115200n8";
35 shunt-resistor = <1000>;
57 #address-cells = <2>;
58 #size-cells = <1>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Darmada-385-clearfog-gtr-l8.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 #include "armada-385-clearfog-gtr.dtsi"
13 pinctrl-names = "default";
14 pinctrl-0 = <&cf_gtr_switch_reset_pins>;
15 reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
18 #address-cells = <1>;
19 #size-cells = <0>;
24 phy-handle = <&switch0phy0>;
30 phy-handle = <&switch0phy1>;
36 phy-handle = <&switch0phy2>;
[all …]
Dls1021a-tsn.dts1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2016-2018 NXP Semiconductors
6 /dts-v1/;
10 model = "NXP LS1021A-TSN Board";
12 sys_mclk: clock-mclk {
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <24576000>;
18 reg_vdda_codec: regulator-3V3 {
19 compatible = "regulator-fixed";
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/dsa/
Dqca8k.txt5 - compatible: should be one of:
9 - #size-cells: must be 0
10 - #address-cells: must be 1
16 port and PHY id, each subnode describing a port needs to have a valid phandle
17 referencing the internal PHY connected to it. The CPU port of this switch is
22 - fixed-link : Fixed-link subnode describing a link to a non-MDIO
24 Documentation/devicetree/bindings/net/fixed-link.txt
27 For QCA8K the 'fixed-link' sub-node supports only the following properties:
29 - 'speed' (integer, mandatory), to indicate the link speed. Accepted
31 - 'full-duplex' (boolean, optional), to indicate that full duplex is
[all …]

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