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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/
Ddwmac-sun8i.txt3 This device is a platform glue layer for stmmac.
7 - compatible: must be one of the following string:
8 "allwinner,sun8i-a83t-emac"
9 "allwinner,sun8i-h3-emac"
10 "allwinner,sun8i-r40-gmac"
11 "allwinner,sun8i-v3s-emac"
12 "allwinner,sun50i-a64-emac"
13 - reg: address and length of the register for the device.
14 - interrupts: interrupt for the device
15 - interrupt-names: must be "macirq"
[all …]
Dphy.txt1 PHY nodes
5 - interrupts : interrupt specifier for the sole interrupt.
6 - reg : The ID number for the phy, usually a small integer
10 - compatible: Compatible list, may contain
11 "ethernet-phy-ieee802.3-c22" or "ethernet-phy-ieee802.3-c45" for
13 specifications. If neither of these are specified, the default is to
16 If the PHY reports an incorrect ID (or none at all) then the
17 "compatible" list may contain an entry with the correct PHY ID in the
18 form: "ethernet-phy-idAAAA.BBBB" where
19 AAAA - The value of the 16 bit Phy Identifier 1 register as
[all …]
Dsnps,dwc-qos-ethernet.txt3 This binding is deprecated, but it continues to be supported, but new
13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
17 Represents the IP core when integrated into the NVIDIA Tegra186 SoC.
18 - "snps,dwc-qos-ethernet-4.10"
19 This combination is deprecated. It should be treated as equivalent to
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
[all …]
Dbrcm,unimac-mdio.txt4 - compatible: should one from "brcm,genet-mdio-v1", "brcm,genet-mdio-v2",
5 "brcm,genet-mdio-v3", "brcm,genet-mdio-v4", "brcm,genet-mdio-v5" or
6 "brcm,unimac-mdio"
7 - reg: address and length of the register set for the device, first one is the
8 base register, and the second one is optional and for indirect accesses to
9 larger than 16-bits MDIO transactions
10 - reg-names: name(s) of the register must be "mdio" and optional "mdio_indir_rw"
11 - #size-cells: must be 1
12 - #address-cells: must be 0
15 - interrupts: must be one if the interrupt is shared with the Ethernet MAC or
[all …]
/kernel/linux/linux-5.10/Documentation/networking/dsa/
Dbcm_sf2.rst5 Broadcom's Starfighter 2 Ethernet switch hardware block is commonly found and
8 - xDSL gateways such as BCM63138
9 - streaming/multimedia Set Top Box such as BCM7445
10 - Cable Modem/residential gateways such as BCM7145/BCM3390
12 The switch is typically deployed in a configuration involving between 5 to 13
13 ports, offering a range of built-in and customizable interfaces:
15 - single integrated Gigabit PHY
16 - quad integrated Gigabit PHY
17 - quad external Gigabit PHY w/ MDIO multiplexer
18 - integrated MoCA PHY
[all …]
/kernel/linux/linux-4.19/Documentation/networking/dsa/
Dbcm_sf2.txt4 Broadcom's Starfighter 2 Ethernet switch hardware block is commonly found and
7 - xDSL gateways such as BCM63138
8 - streaming/multimedia Set Top Box such as BCM7445
9 - Cable Modem/residential gateways such as BCM7145/BCM3390
11 The switch is typically deployed in a configuration involving between 5 to 13
12 ports, offering a range of built-in and customizable interfaces:
14 - single integrated Gigabit PHY
15 - quad integrated Gigabit PHY
16 - quad external Gigabit PHY w/ MDIO multiplexer
17 - integrated MoCA PHY
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/dsa/
Db53.txt6 - compatible: For external switch chips, compatible string must be exactly one
18 "brcm,bcm11360-srab" and the mandatory "brcm,cygnus-srab" string
20 For the BCM5310x SoCs with an integrated switch, must be one of:
21 "brcm,bcm53010-srab"
22 "brcm,bcm53011-srab"
23 "brcm,bcm53012-srab"
24 "brcm,bcm53018-srab"
25 "brcm,bcm53019-srab" and the mandatory "brcm,bcm5301x-srab" string
27 For the BCM5831X/BCM1140x SoCs with an integrated switch, must be one of:
28 "brcm,bcm11404-srab"
[all …]
Dvitesse,vsc73xx.txt9 Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
10 Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
11 Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
12 Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
16 If SPI interface is used, the device tree node is an SPI device so it must
17 reside inside a SPI bus device tree node, see spi/spi-bus.txt
19 When the chip is connected to a parallel memory bus and work in memory-mapped
20 I/O mode, a platform device is used to represent the vsc73xx. In this case it
25 - compatible: must be exactly one of:
30 - gpio-controller: indicates that this switch is also a GPIO controller,
[all …]
Dmt7530.txt6 - compatible: may be compatible = "mediatek,mt7530"
9 - #address-cells: Must be 1.
10 - #size-cells: Must be 0.
11 - mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
12 on multi-chip module belong to MT7623A has or the remotely standalone
15 If compatible mediatek,mt7530 is set then the following properties are required
17 - core-supply: Phandle to the regulator node necessary for the core power.
18 - io-supply: Phandle to the regulator node necessary for the I/O power.
19 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
22 If the property mediatek,mcm isn't defined, following property is required
[all …]
Dqca8k.txt5 - compatible: should be one of:
9 - #size-cells: must be 0
10 - #address-cells: must be 1
14 - reset-gpios: GPIO to be used to reset the whole device
18 The integrated switch subnode should be specified according to the binding
19 described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external
20 mdio-bus each subnode describing a port needs to have a valid phandle
21 referencing the internal PHY it is connected to. This is because there's no
22 N:N mapping of port and PHY id.
24 Don't use mixed external and internal mdio-bus configurations, as this is
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Generic Binding
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
16 # case, the node name is the one we want to match on, while the
[all …]
Dsnps,dwc-qos-ethernet.txt3 This binding is deprecated, but it continues to be supported, but new
13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
17 Represents the IP core when integrated into the NVIDIA Tegra186 SoC.
18 - "snps,dwc-qos-ethernet-4.10"
19 This combination is deprecated. It should be treated as equivalent to
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
[all …]
Dallwinner,sun8i-a83t-emac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - const: allwinner,sun8i-a83t-emac
17 - const: allwinner,sun8i-h3-emac
18 - const: allwinner,sun8i-r40-emac
19 - const: allwinner,sun8i-v3s-emac
[all …]
Dbrcm,unimac-mdio.txt4 - compatible: should one from "brcm,genet-mdio-v1", "brcm,genet-mdio-v2",
5 "brcm,genet-mdio-v3", "brcm,genet-mdio-v4", "brcm,genet-mdio-v5" or
6 "brcm,unimac-mdio"
7 - reg: address and length of the register set for the device, first one is the
8 base register, and the second one is optional and for indirect accesses to
9 larger than 16-bits MDIO transactions
10 - reg-names: name(s) of the register must be "mdio" and optional "mdio_indir_rw"
11 - #size-cells: must be 1
12 - #address-cells: must be 0
15 - interrupts: must be one if the interrupt is shared with the Ethernet MAC or
[all …]
Dcortina,gemini-ethernet.txt4 This ethernet controller is found in the Gemini SoC family:
9 - compatible: must be "cortina,gemini-ethernet"
10 - reg: must contain the global registers and the V-bit and A-bit
12 - syscon: a phandle to the system controller
13 - #address-cells: must be specified, must be <1>
14 - #size-cells: must be specified, must be <1>
15 - ranges: should be state like this giving a 1:1 address translation
23 - port0: contains the resources for ethernet port 0
24 - port1: contains the resources for ethernet port 1
27 - compatible: must be "cortina,gemini-ethernet-port"
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/wiznet/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
26 W5100 is a single chip with integrated 10/100 Ethernet MAC,
27 PHY and hardware TCP/IP stack, but this driver is limited to
28 the MAC and PHY functions only, onchip TCP/IP is unused.
39 W5300 is a single chip with integrated 10/100 Ethernet MAC,
40 PHY and hardware TCP/IP stack, but this driver is limited to
41 the MAC and PHY functions only, onchip TCP/IP is unused.
55 after mapping to Memory-Mapped I/O space.
62 which are directly mapped to Memory-Mapped I/O space.
67 If interface mode is unknown in compile time, it can be selected
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/wiznet/
DKconfig9 ---help---
22 ---help---
25 W5100 is a single chip with integrated 10/100 Ethernet MAC,
26 PHY and hardware TCP/IP stack, but this driver is limited to
27 the MAC and PHY functions only, onchip TCP/IP is unused.
35 ---help---
38 W5300 is a single chip with integrated 10/100 Ethernet MAC,
39 PHY and hardware TCP/IP stack, but this driver is limited to
40 the MAC and PHY functions only, onchip TCP/IP is unused.
52 ---help---
[all …]
/kernel/linux/linux-5.10/drivers/net/phy/
Dintel-xway.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/phy.h>
17 #define XWAY_MDIO_LED_LED3_EN BIT(11) /* Enable the integrated function of LED3 */
18 #define XWAY_MDIO_LED_LED2_EN BIT(10) /* Enable the integrated function of LED2 */
19 #define XWAY_MDIO_LED_LED1_EN BIT(9) /* Enable the integrated function of LED1 */
20 #define XWAY_MDIO_LED_LED0_EN BIT(8) /* Enable the integrated function of LED0 */
27 #define XWAY_MDIO_INIT_WOL BIT(15) /* Wake-On-LAN */
31 #define XWAY_MDIO_INIT_ANE BIT(11) /* Auto-Neg error */
32 #define XWAY_MDIO_INIT_ANC BIT(10) /* Auto-Neg complete */
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # PHY Layer Configuration
12 PHYlink models the link between the PHY and MAC, allowing fixed
17 tristate "PHY Device support and infrastructure"
22 Ethernet controllers are usually attached to PHY
24 managing PHY devices.
35 Adds support for a set of LED trigger events per-PHY. Link
38 supported by the PHY and also a one common "link" trigger as a
39 logical-or of all the link speed ones.
41 <mii bus id>:<phy>:<speed>
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/dsa/
Dvitesse,vsc73xx.txt9 Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
10 Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
11 Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
12 Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
14 The device tree node is an SPI device so it must reside inside a SPI bus
15 device tree node, see spi/spi-bus.txt
19 - compatible: must be exactly one of:
24 - gpio-controller: indicates that this switch is also a GPIO controller,
26 - #gpio-cells: this must be set to <2> and indicates that we are a twocell
31 - reset-gpios: a handle to a GPIO line that can issue reset of the chip.
[all …]
Dqca8k.txt5 - compatible: should be one of:
9 - #size-cells: must be 0
10 - #address-cells: must be 1
14 The integrated switch subnode should be specified according to the binding
16 port and PHY id, each subnode describing a port needs to have a valid phandle
17 referencing the internal PHY connected to it. The CPU port of this switch is
22 - fixed-link : Fixed-link subnode describing a link to a non-MDIO
24 Documentation/devicetree/bindings/net/fixed-link.txt
27 For QCA8K the 'fixed-link' sub-node supports only the following properties:
29 - 'speed' (integer, mandatory), to indicate the link speed. Accepted
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Drk3228-evb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
9 compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
16 vcc_phy: vcc-phy-regulator {
17 compatible = "regulator-fixed";
18 enable-active-high;
19 regulator-name = "vcc_phy";
20 regulator-min-microvolt = <1800000>;
21 regulator-max-microvolt = <1800000>;
22 regulator-always-on;
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Drk3228-evb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
9 compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
16 vcc_phy: vcc-phy-regulator {
17 compatible = "regulator-fixed";
18 enable-active-high;
19 regulator-name = "vcc_phy";
20 regulator-min-microvolt = <1800000>;
21 regulator-max-microvolt = <1800000>;
22 regulator-always-on;
[all …]
/kernel/linux/linux-4.19/drivers/net/phy/
DKconfig2 # PHY Layer Configuration
15 This internal symbol is used for link time dependencies and it
16 reflects whether the mdio_bus/mdio_device code is built as a
17 loadable module or built-in.
53 to a parent bus. Switching between child busses is done by
75 selection is under the control of GPIO lines.
78 tristate "MMIO device-controlled MDIO bus multiplexers"
83 are controlled via a simple memory-mapped device, like an FPGA.
85 parent bus. Child bus selection is under the control of one of
94 tristate "GPIO lib-based bitbanged MDIO buses"
[all …]
Dintel-xway.c3 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
5 * This program is free software; you can redistribute it and/or modify
10 * This program is distributed in the hope that it will be useful,
18 #include <linux/phy.h>
24 #define XWAY_MDIO_INIT_WOL BIT(15) /* Wake-On-LAN */
28 #define XWAY_MDIO_INIT_ANE BIT(11) /* Auto-Neg error */
29 #define XWAY_MDIO_INIT_ANC BIT(10) /* Auto-Neg complete */
30 #define XWAY_MDIO_INIT_ADSC BIT(5) /* Link auto-downspeed detect */
39 #define ADVERTISED_MPD BIT(10) /* Multi-port device */
180 * In most cases only one LED is connected to this phy, so in xway_gphy_config_init()
[all …]

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