| /kernel/linux/linux-5.10/drivers/nfc/s3fwrn5/ |
| D | i2c.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
34 enum s3fwrn5_mode mode; member
40 struct s3fwrn5_i2c_phy *phy = phy_id; in s3fwrn5_i2c_set_wake() local
42 mutex_lock(&phy->mutex); in s3fwrn5_i2c_set_wake()
43 gpio_set_value(phy->gpio_fw_wake, wake); in s3fwrn5_i2c_set_wake()
45 mutex_unlock(&phy->mutex); in s3fwrn5_i2c_set_wake()
48 static void s3fwrn5_i2c_set_mode(void *phy_id, enum s3fwrn5_mode mode) in s3fwrn5_i2c_set_mode() argument
50 struct s3fwrn5_i2c_phy *phy = phy_id; in s3fwrn5_i2c_set_mode() local
52 mutex_lock(&phy->mutex); in s3fwrn5_i2c_set_mode()
54 if (phy->mode == mode) in s3fwrn5_i2c_set_mode()
[all …]
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| /kernel/linux/linux-4.19/drivers/nfc/s3fwrn5/ |
| D | i2c.c | 45 enum s3fwrn5_mode mode; member
51 struct s3fwrn5_i2c_phy *phy = phy_id; in s3fwrn5_i2c_set_wake() local
53 mutex_lock(&phy->mutex); in s3fwrn5_i2c_set_wake()
54 gpio_set_value(phy->gpio_fw_wake, wake); in s3fwrn5_i2c_set_wake()
56 mutex_unlock(&phy->mutex); in s3fwrn5_i2c_set_wake()
59 static void s3fwrn5_i2c_set_mode(void *phy_id, enum s3fwrn5_mode mode) in s3fwrn5_i2c_set_mode() argument
61 struct s3fwrn5_i2c_phy *phy = phy_id; in s3fwrn5_i2c_set_mode() local
63 mutex_lock(&phy->mutex); in s3fwrn5_i2c_set_mode()
65 if (phy->mode == mode) in s3fwrn5_i2c_set_mode()
68 phy->mode = mode; in s3fwrn5_i2c_set_mode()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/hisilicon/kirin/ |
| D | dw_drm_dsi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2014-2016 Hisilicon Limited.
88 struct mipi_phy_params phy; member
121 static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy) in dsi_calc_phy_rate() argument
151 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; in dsi_calc_phy_rate()
152 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel; in dsi_calc_phy_rate()
154 if (phy->hstx_ckg_sel <= 7 && in dsi_calc_phy_rate()
155 phy->hstx_ckg_sel >= 4) in dsi_calc_phy_rate()
156 q_pll = 0x10 >> (7 - phy->hstx_ckg_sel); in dsi_calc_phy_rate()
190 phy->pll_fbd_p = 0; in dsi_calc_phy_rate()
[all …]
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| /kernel/linux/linux-4.19/drivers/gpu/drm/hisilicon/kirin/ |
| D | dw_drm_dsi.c | 5 * Copyright (c) 2014-2016 Hisilicon Limited.
86 struct mipi_phy_params phy; member
119 static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy) in dsi_calc_phy_rate() argument
149 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; in dsi_calc_phy_rate()
150 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel; in dsi_calc_phy_rate()
152 if (phy->hstx_ckg_sel <= 7 && in dsi_calc_phy_rate()
153 phy->hstx_ckg_sel >= 4) in dsi_calc_phy_rate()
154 q_pll = 0x10 >> (7 - phy->hstx_ckg_sel); in dsi_calc_phy_rate()
188 phy->pll_fbd_p = 0; in dsi_calc_phy_rate()
189 phy->pll_pre_div1p = 1; in dsi_calc_phy_rate()
[all …]
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| /kernel/linux/linux-5.10/include/linux/phy/ |
| D | phy.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * phy.h -- generic phy header file
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
19 #include <linux/phy/phy-dp.h>
20 #include <linux/phy/phy-mipi-dphy.h>
22 struct phy;
48 * union phy_configure_opts - Opaque generic phy configuration
51 * the MIPI_DPHY phy mode.
61 * struct phy_ops - set of function pointers for performing phy operations
62 * @init: operation to be performed for initializing phy
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/marvell/ |
| D | phy-mvebu-a3700-comphy.c | 1 // SPDX-License-Identifier: GPL-2.0
9 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
13 #include <linux/arm-smccc.h>
18 #include <linux/phy.h>
19 #include <linux/phy/phy.h>
50 #define COMPHY_FW_MODE(mode) ((mode) << 12) argument
51 #define COMPHY_FW_NET(mode, idx, speed) (COMPHY_FW_MODE(mode) | \ argument
54 #define COMPHY_FW_PCIE(mode, idx, speed, width) (COMPHY_FW_NET(mode, idx, speed) | \ argument
59 enum phy_mode mode; member
68 .mode = _mode, \
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/hisilicon/ |
| D | phy-histb-combphy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
17 #include <linux/phy/phy.h>
20 #include <dt-bindings/phy/phy.h>
48 struct phy *phy; member
49 struct histb_combphy_mode mode; member
55 void __iomem *reg = priv->mmio + COMBPHY_CFG_REG; in nano_register_write()
73 static int is_mode_fixed(struct histb_combphy_mode *mode) in is_mode_fixed() argument
75 return (mode->fixed != PHY_NONE) ? true : false; in is_mode_fixed()
80 struct histb_combphy_mode *mode = &priv->mode; in histb_combphy_set_mode() local
[all …]
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| /kernel/linux/linux-4.19/drivers/phy/hisilicon/ |
| D | phy-histb-combphy.c | 4 * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
20 #include <linux/phy/phy.h>
23 #include <dt-bindings/phy/phy.h>
51 struct phy *phy; member
52 struct histb_combphy_mode mode; member
58 void __iomem *reg = priv->mmio + COMBPHY_CFG_REG; in nano_register_write()
76 static int is_mode_fixed(struct histb_combphy_mode *mode) in is_mode_fixed() argument
78 return (mode->fixed != PHY_NONE) ? true : false; in is_mode_fixed()
83 struct histb_combphy_mode *mode = &priv->mode; in histb_combphy_set_mode() local
84 struct regmap *syscon = priv->syscon; in histb_combphy_set_mode()
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/ti/ |
| D | phy-ti-pipe3.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/phy/phy.h>
19 #include <linux/phy/omap_control_phy.h>
181 enum pipe3_mode mode; member
206 enum pipe3_mode mode; member
212 .mode = PIPE3_MODE_USBSS,
215 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
238 .mode = PIPE3_MODE_SATA,
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | phy-hi3798cv200-combphy.txt | 1 HiSilicon STB PCIE/SATA/USB3 PHY
4 - compatible: Should be "hisilicon,hi3798cv200-combphy"
5 - reg: Should be the address space for COMBPHY configuration and state
8 - #phy-cells: Should be 1. The cell number is used to select the phy mode
9 as defined in <dt-bindings/phy/phy.h>.
10 - clocks: The phandle to clock provider and clock specifier pair.
11 - resets: The phandle to reset controller and reset specifier pair.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
16 - hisilicon,fixed-mode: If the phy device doesn't support mode select
17 but a fixed mode setting, the property should be present to specify
[all …]
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| D | ti,phy-gmii-sel.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: CPSW Port's Interface Mode Selection PHY Tree Bindings
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 The interface mode is selected by configuring the MII mode selection register(s)
20 +--------------+
21 +-------------------------------+ |SCM |
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/phy/ |
| D | phy-hi3798cv200-combphy.txt | 1 HiSilicon STB PCIE/SATA/USB3 PHY
4 - compatible: Should be "hisilicon,hi3798cv200-combphy"
5 - reg: Should be the address space for COMBPHY configuration and state
8 - #phy-cells: Should be 1. The cell number is used to select the phy mode
9 as defined in <dt-bindings/phy/phy.h>.
10 - clocks: The phandle to clock provider and clock specifier pair.
11 - resets: The phandle to reset controller and reset specifier pair.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
16 - hisilicon,fixed-mode: If the phy device doesn't support mode select
17 but a fixed mode setting, the property should be present to specify
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/amlogic/ |
| D | phy-meson-axg-mipi-pcie-analog.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Amlogic AXG MIPI + PCIE analog PHY driver
8 #include <linux/phy/phy.h>
11 #include <dt-bindings/phy/phy.h>
34 #define HHI_MIPI_CNTL2_CH_EN(n) BIT(15 - (n))
38 struct phy *phy; member
39 unsigned int mode; member
50 static int phy_axg_mipi_pcie_analog_power_on(struct phy *phy) in phy_axg_mipi_pcie_analog_power_on() argument
52 struct phy_axg_mipi_pcie_analog_priv *priv = phy_get_drvdata(phy); in phy_axg_mipi_pcie_analog_power_on()
55 if (priv->mode != PHY_TYPE_PCIE) in phy_axg_mipi_pcie_analog_power_on()
[all …]
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| D | phy-meson-gxl-usb2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Meson GXL and GXM USB2 PHY driver
15 #include <linux/phy/phy.h>
18 /* bits [31:27] are read-only */
66 /* bits [31:14] are read-only */
94 enum phy_mode mode; member
107 static int phy_meson_gxl_usb2_init(struct phy *phy) in phy_meson_gxl_usb2_init() argument
109 struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy); in phy_meson_gxl_usb2_init()
112 ret = reset_control_reset(priv->reset); in phy_meson_gxl_usb2_init()
116 ret = clk_prepare_enable(priv->clk); in phy_meson_gxl_usb2_init()
[all …]
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| D | phy-meson-g12a-usb3-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Amlogic G12A USB3 + PCIE Combo PHY driver
15 #include <linux/phy/phy.h>
19 #include <dt-bindings/phy/phy.h>
60 struct phy *phy; member
61 unsigned int mode; member
79 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_addr()
80 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_addr()
82 regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_ADDR); in phy_g12a_usb3_pcie_cr_bus_addr()
84 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, in phy_g12a_usb3_pcie_cr_bus_addr()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/dsa/ |
| D | mt7530.txt | 6 - compatible: may be compatible = "mediatek,mt7530"
9 - #address-cells: Must be 1.
10 - #size-cells: Must be 0.
11 - mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
12 on multi-chip module belong to MT7623A has or the remotely standalone
17 - core-supply: Phandle to the regulator node necessary for the core power.
18 - io-supply: Phandle to the regulator node necessary for the I/O power.
19 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
24 - reset-gpios: Should be a gpio specifier for a reset line.
28 - resets : Phandle pointing to the system reset controller with
[all …]
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| D | sja1105.txt | 6 - compatible:
8 - "nxp,sja1105e"
9 - "nxp,sja1105t"
10 - "nxp,sja1105p"
11 - "nxp,sja1105q"
12 - "nxp,sja1105r"
13 - "nxp,sja1105s"
18 and the non-SGMII devices, while pin-compatible, are not equal in terms
24 - sja1105,role-mac:
25 - sja1105,role-phy:
[all …]
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| /kernel/linux/linux-4.19/drivers/phy/amlogic/ |
| D | phy-meson-gxl-usb3.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Meson GXL USB3 PHY and OTG mode detection driver
13 #include <linux/phy/phy.h>
78 /* read-only register */
85 enum phy_mode mode; member
98 static int phy_meson_gxl_usb3_power_on(struct phy *phy) in phy_meson_gxl_usb3_power_on() argument
100 struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy); in phy_meson_gxl_usb3_power_on()
102 regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_EN_0, in phy_meson_gxl_usb3_power_on()
104 regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_EN_1, in phy_meson_gxl_usb3_power_on()
106 regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_TH_MASK, in phy_meson_gxl_usb3_power_on()
[all …]
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| D | phy-meson-gxl-usb2.c | 2 * Meson GXL and GXM USB2 PHY driver
21 #include <linux/phy/phy.h>
24 /* bits [31:27] are read-only */
72 /* bits [31:14] are read-only */
100 enum phy_mode mode; member
113 static int phy_meson_gxl_usb2_init(struct phy *phy) in phy_meson_gxl_usb2_init() argument
115 struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy); in phy_meson_gxl_usb2_init()
118 ret = reset_control_reset(priv->reset); in phy_meson_gxl_usb2_init()
122 ret = clk_prepare_enable(priv->clk); in phy_meson_gxl_usb2_init()
129 static int phy_meson_gxl_usb2_exit(struct phy *phy) in phy_meson_gxl_usb2_exit() argument
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/ |
| D | t1040rdb.dts | 4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t104xsi-pre.dtsi"
49 fixed-link = <0 1 1000 0 0>;
50 phy-connection-type = "sgmii";
54 fixed-link = <1 1 1000 0 0>;
55 phy-connection-type = "sgmii";
59 phy-handle = <&phy_sgmii_2>;
60 phy-connection-type = "sgmii";
64 phy_sgmii_2: ethernet-phy@3 {
68 /* VSC8514 QSGMII PHY */
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | ti,dp83822.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI DP83822 ethernet PHY
11 - Dan Murphy <dmurphy@ti.com>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
20 Specifications about the Ethernet PHY can be found at:
24 - $ref: "ethernet-phy.yaml#"
[all …]
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| /kernel/linux/linux-5.10/drivers/media/platform/omap3isp/ |
| D | ispcsiphy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - CSI PHY module
23 static void csiphy_routing_cfg_3630(struct isp_csiphy *phy, in csiphy_routing_cfg_3630() argument
28 u32 shift, mode; in csiphy_routing_cfg_3630() local
30 regmap_read(phy->isp->syscon, phy->isp->syscon_offset, ®); in csiphy_routing_cfg_3630()
41 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY; in csiphy_routing_cfg_3630()
49 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY; in csiphy_routing_cfg_3630()
53 /* Select data/clock or data/strobe mode for CCP2 */ in csiphy_routing_cfg_3630()
57 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_STROBE; in csiphy_routing_cfg_3630()
59 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_CLOCK; in csiphy_routing_cfg_3630()
[all …]
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| /kernel/linux/linux-4.19/drivers/media/platform/omap3isp/ |
| D | ispcsiphy.c | 4 * TI OMAP3 ISP - CSI PHY module
26 static void csiphy_routing_cfg_3630(struct isp_csiphy *phy, in csiphy_routing_cfg_3630() argument
31 u32 shift, mode; in csiphy_routing_cfg_3630() local
33 regmap_read(phy->isp->syscon, phy->isp->syscon_offset, ®); in csiphy_routing_cfg_3630()
44 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY; in csiphy_routing_cfg_3630()
52 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY; in csiphy_routing_cfg_3630()
56 /* Select data/clock or data/strobe mode for CCP2 */ in csiphy_routing_cfg_3630()
60 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_STROBE; in csiphy_routing_cfg_3630()
62 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_CLOCK; in csiphy_routing_cfg_3630()
66 reg |= mode << shift; in csiphy_routing_cfg_3630()
[all …]
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| /kernel/linux/linux-5.10/drivers/net/ |
| D | sungem_phy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * PHY drivers for the sungem ethernet driver.
7 * (c) 2002-2007, Benjamin Herrenscmidt (benh@kernel.crashing.org)
10 * - Add support for PHYs that provide an IRQ line
11 * - Eventually moved the entire polling state machine in
14 * - On LXT971 & BCM5201, Apple uses some chip specific regs
17 * - Apple has some additional power management code for some
39 /* Link modes of the BCM5400 PHY */
51 static inline int __sungem_phy_read(struct mii_phy* phy, int id, int reg) in __sungem_phy_read() argument
53 return phy->mdio_read(phy->dev, id, reg); in __sungem_phy_read()
[all …]
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| /kernel/linux/linux-4.19/drivers/net/ |
| D | sungem_phy.c | 2 * PHY drivers for the sungem ethernet driver.
6 * (c) 2002-2007, Benjamin Herrenscmidt (benh@kernel.crashing.org)
9 * - Add support for PHYs that provide an IRQ line
10 * - Eventually moved the entire polling state machine in
13 * - On LXT971 & BCM5201, Apple uses some chip specific regs
16 * - Apple has some additional power management code for some
38 /* Link modes of the BCM5400 PHY */
50 static inline int __sungem_phy_read(struct mii_phy* phy, int id, int reg) in __sungem_phy_read() argument
52 return phy->mdio_read(phy->dev, id, reg); in __sungem_phy_read()
55 static inline void __sungem_phy_write(struct mii_phy* phy, int id, int reg, int val) in __sungem_phy_write() argument
[all …]
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