| /kernel/linux/linux-4.19/drivers/irqchip/ |
| D | irq-mvebu-pic.c | 35 static void mvebu_pic_reset(struct mvebu_pic *pic) in mvebu_pic_reset() argument
38 writel(0, pic->base + PIC_MASK); in mvebu_pic_reset()
39 writel(PIC_MAX_IRQ_MASK, pic->base + PIC_CAUSE); in mvebu_pic_reset()
44 struct mvebu_pic *pic = irq_data_get_irq_chip_data(d); in mvebu_pic_eoi_irq() local
46 writel(1 << d->hwirq, pic->base + PIC_CAUSE); in mvebu_pic_eoi_irq()
51 struct mvebu_pic *pic = irq_data_get_irq_chip_data(d); in mvebu_pic_mask_irq() local
54 reg = readl(pic->base + PIC_MASK); in mvebu_pic_mask_irq()
56 writel(reg, pic->base + PIC_MASK); in mvebu_pic_mask_irq()
61 struct mvebu_pic *pic = irq_data_get_irq_chip_data(d); in mvebu_pic_unmask_irq() local
64 reg = readl(pic->base + PIC_MASK); in mvebu_pic_unmask_irq()
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| D | irq-or1k-pic.c | 17 /* OR1K PIC implementation */
52 * There are two oddities with the OR1200 PIC implementation:
70 .name = "or1k-PIC-level",
81 .name = "or1k-PIC-edge",
93 .name = "or1200-PIC",
128 struct or1k_pic_dev *pic = d->host_data; in or1k_map() local
130 irq_set_chip_and_handler(irq, &pic->chip, pic->handle); in or1k_map()
131 irq_set_status_flags(irq, pic->flags); in or1k_map()
142 * This sets up the IRQ domain for the PIC built in to the OpenRISC
147 struct or1k_pic_dev *pic) in or1k_pic_init() argument
[all …]
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| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-mvebu-pic.c | 35 static void mvebu_pic_reset(struct mvebu_pic *pic) in mvebu_pic_reset() argument
38 writel(0, pic->base + PIC_MASK); in mvebu_pic_reset()
39 writel(PIC_MAX_IRQ_MASK, pic->base + PIC_CAUSE); in mvebu_pic_reset()
44 struct mvebu_pic *pic = irq_data_get_irq_chip_data(d); in mvebu_pic_eoi_irq() local
46 writel(1 << d->hwirq, pic->base + PIC_CAUSE); in mvebu_pic_eoi_irq()
51 struct mvebu_pic *pic = irq_data_get_irq_chip_data(d); in mvebu_pic_mask_irq() local
54 reg = readl(pic->base + PIC_MASK); in mvebu_pic_mask_irq()
56 writel(reg, pic->base + PIC_MASK); in mvebu_pic_mask_irq()
61 struct mvebu_pic *pic = irq_data_get_irq_chip_data(d); in mvebu_pic_unmask_irq() local
64 reg = readl(pic->base + PIC_MASK); in mvebu_pic_unmask_irq()
[all …]
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| D | irq-or1k-pic.c | 13 /* OR1K PIC implementation */
48 * There are two oddities with the OR1200 PIC implementation:
66 .name = "or1k-PIC-level",
77 .name = "or1k-PIC-edge",
89 .name = "or1200-PIC",
124 struct or1k_pic_dev *pic = d->host_data; in or1k_map() local
126 irq_set_chip_and_handler(irq, &pic->chip, pic->handle); in or1k_map()
127 irq_set_status_flags(irq, pic->flags); in or1k_map()
138 * This sets up the IRQ domain for the PIC built in to the OpenRISC
143 struct or1k_pic_dev *pic) in or1k_pic_init() argument
[all …]
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| /kernel/linux/linux-5.10/arch/c6x/platforms/ |
| D | megamod-pic.c | 16 #include <asm/megamod-pic.h>
59 struct megamod_pic *pic; member
67 struct megamod_pic *pic = irq_data_get_irq_chip_data(data); in mask_megamod() local
69 u32 __iomem *evtmask = &pic->regs->evtmask[src / 32]; in mask_megamod()
71 raw_spin_lock(&pic->lock); in mask_megamod()
73 raw_spin_unlock(&pic->lock); in mask_megamod()
78 struct megamod_pic *pic = irq_data_get_irq_chip_data(data); in unmask_megamod() local
80 u32 __iomem *evtmask = &pic->regs->evtmask[src / 32]; in unmask_megamod()
82 raw_spin_lock(&pic->lock); in unmask_megamod()
84 raw_spin_unlock(&pic->lock); in unmask_megamod()
[all …]
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| /kernel/linux/linux-4.19/arch/c6x/platforms/ |
| D | megamod-pic.c | 19 #include <asm/megamod-pic.h>
62 struct megamod_pic *pic; member
70 struct megamod_pic *pic = irq_data_get_irq_chip_data(data); in mask_megamod() local
72 u32 __iomem *evtmask = &pic->regs->evtmask[src / 32]; in mask_megamod()
74 raw_spin_lock(&pic->lock); in mask_megamod()
76 raw_spin_unlock(&pic->lock); in mask_megamod()
81 struct megamod_pic *pic = irq_data_get_irq_chip_data(data); in unmask_megamod() local
83 u32 __iomem *evtmask = &pic->regs->evtmask[src / 32]; in unmask_megamod()
85 raw_spin_lock(&pic->lock); in unmask_megamod()
87 raw_spin_unlock(&pic->lock); in unmask_megamod()
[all …]
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| /kernel/linux/linux-5.10/arch/mips/boot/dts/loongson/ |
| D | ls7a-pch.dtsi | 13 pic: interrupt-controller@10000000 { label
14 compatible = "loongson,pch-pic-1.0";
18 loongson,pic-base-vec = <0>;
26 interrupt-parent = <&pic>;
36 interrupt-parent = <&pic>;
46 interrupt-parent = <&pic>;
56 interrupt-parent = <&pic>;
83 interrupt-parent = <&pic>;
94 interrupt-parent = <&pic>;
105 interrupt-parent = <&pic>;
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/ |
| D | open-pic.txt | 1 * Open PIC Binding
4 representation of an Open PIC compliant interrupt controller. This binding is
5 based on the binding defined for Open PIC in [1] and is a superset of that
13 - compatible: Specifies the compatibility list for the PIC. The type
14 shall be <string> and the value shall include "open-pic".
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
20 as an Open PIC. No property value shall be defined.
31 - pic-no-reset: The presence of this property indicates that the PIC
55 * An Open PIC interrupt controller
57 mpic: pic@40000 {
[all …]
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| D | ti,c64x+megamod-pic.txt | 13 - compatible: Should be "ti,c64x+core-pic";
26 compatible = "ti,c64x+core-pic";
33 The megamodule PIC consists of four interrupt mupliplexers each of which
35 may be cascaded into the core interrupt controller. The megamodule PIC
45 - compatible: "ti,c64x+megamod-pic"
55 - ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core
68 interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will
75 compatible = "ti,c64x+megamod-pic";
89 compatible = "ti,c64x+megamod-pic";
95 ti,c64x+megamod-pic-mux = < 0 0 0 0
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| D | opencores,or1k-pic.txt | 5 - compatible : should be "opencores,or1k-pic-level" for variants with
6 level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with
7 edge triggered interrupt lines or "opencores,or1200-pic" for machines
10 "opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic",
20 compatible = "opencores,or1k-pic-level";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | open-pic.txt | 1 * Open PIC Binding
4 representation of an Open PIC compliant interrupt controller. This binding is
5 based on the binding defined for Open PIC in [1] and is a superset of that
13 - compatible: Specifies the compatibility list for the PIC. The type
14 shall be <string> and the value shall include "open-pic".
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
20 as an Open PIC. No property value shall be defined.
31 - pic-no-reset: The presence of this property indicates that the PIC
55 * An Open PIC interrupt controller
57 mpic: pic@40000 {
[all …]
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| D | loongson,pch-pic.yaml | 4 $id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#"
7 title: Loongson PCH PIC Controller
19 const: loongson,pch-pic-1.0
24 loongson,pic-base-vec:
27 to PCH PIC.
40 - loongson,pic-base-vec
49 pic: interrupt-controller@10000000 {
50 compatible = "loongson,pch-pic-1.0";
54 loongson,pic-base-vec = <64>;
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| D | ti,c64x+megamod-pic.txt | 13 - compatible: Should be "ti,c64x+core-pic";
26 compatible = "ti,c64x+core-pic";
33 The megamodule PIC consists of four interrupt mupliplexers each of which
35 may be cascaded into the core interrupt controller. The megamodule PIC
45 - compatible: "ti,c64x+megamod-pic"
55 - ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core
68 interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will
75 compatible = "ti,c64x+megamod-pic";
89 compatible = "ti,c64x+megamod-pic";
95 ti,c64x+megamod-pic-mux = < 0 0 0 0
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| D | opencores,or1k-pic.txt | 5 - compatible : should be "opencores,or1k-pic-level" for variants with
6 level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with
7 edge triggered interrupt lines or "opencores,or1200-pic" for machines
10 "opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic",
20 compatible = "opencores,or1k-pic-level";
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| /kernel/linux/linux-5.10/arch/powerpc/platforms/cell/ |
| D | spider-pic.c | 63 static void __iomem *spider_get_irq_config(struct spider_pic *pic, in spider_get_irq_config() argument
66 return pic->regs + TIR_CFGA + 8 * src; in spider_get_irq_config()
71 struct spider_pic *pic = spider_irq_data_to_pic(d); in spider_unmask_irq() local
72 void __iomem *cfg = spider_get_irq_config(pic, irqd_to_hwirq(d)); in spider_unmask_irq()
79 struct spider_pic *pic = spider_irq_data_to_pic(d); in spider_mask_irq() local
80 void __iomem *cfg = spider_get_irq_config(pic, irqd_to_hwirq(d)); in spider_mask_irq()
87 struct spider_pic *pic = spider_irq_data_to_pic(d); in spider_ack_irq() local
100 out_be32(pic->regs + TIR_EDC, 0x100 | (src & 0xf)); in spider_ack_irq()
106 struct spider_pic *pic = spider_irq_data_to_pic(d); in spider_set_irq_type() local
108 void __iomem *cfg = spider_get_irq_config(pic, hw); in spider_set_irq_type()
[all …]
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| /kernel/linux/linux-4.19/arch/powerpc/platforms/cell/ |
| D | spider-pic.c | 76 static void __iomem *spider_get_irq_config(struct spider_pic *pic, in spider_get_irq_config() argument
79 return pic->regs + TIR_CFGA + 8 * src; in spider_get_irq_config()
84 struct spider_pic *pic = spider_irq_data_to_pic(d); in spider_unmask_irq() local
85 void __iomem *cfg = spider_get_irq_config(pic, irqd_to_hwirq(d)); in spider_unmask_irq()
92 struct spider_pic *pic = spider_irq_data_to_pic(d); in spider_mask_irq() local
93 void __iomem *cfg = spider_get_irq_config(pic, irqd_to_hwirq(d)); in spider_mask_irq()
100 struct spider_pic *pic = spider_irq_data_to_pic(d); in spider_ack_irq() local
113 out_be32(pic->regs + TIR_EDC, 0x100 | (src & 0xf)); in spider_ack_irq()
119 struct spider_pic *pic = spider_irq_data_to_pic(d); in spider_set_irq_type() local
121 void __iomem *cfg = spider_get_irq_config(pic, hw); in spider_set_irq_type()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | v3-v360epc-pci.txt | 39 interrupt-parent = <&pic>;
56 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
57 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
58 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
59 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
61 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
62 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
63 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
64 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
66 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/pci/ |
| D | v3-v360epc-pci.txt | 39 interrupt-parent = <&pic>;
56 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
57 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
58 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
59 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
61 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
62 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
63 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
64 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
66 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
[all …]
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | integratorap.dts | 111 interrupt-parent = <&pic>;
152 pic: pic@14000000 { label
163 interrupt-parent = <&pic>;
180 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
181 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
182 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
183 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
185 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
186 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
187 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
[all …]
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| /kernel/linux/linux-4.19/arch/ia64/sn/pci/pcibr/ |
| D | pcibr_reg.c | 15 #include <asm/sn/pic.h>
20 struct pic pic; member
36 __sn_clrq_relaxed(&ptr->pic.p_wid_control, bits); in pcireg_control_bit_clr()
56 __sn_setq_relaxed(&ptr->pic.p_wid_control, bits); in pcireg_control_bit_set()
80 ret = __sn_readq_relaxed(&ptr->pic.p_wid_tflush); in pcireg_tflush_get()
110 ret = __sn_readq_relaxed(&ptr->pic.p_int_status); in pcireg_intr_status_get()
134 __sn_clrq_relaxed(&ptr->pic.p_int_enable, bits); in pcireg_intr_enable_bit_clr()
154 __sn_setq_relaxed(&ptr->pic.p_int_enable, bits); in pcireg_intr_enable_bit_set()
181 __sn_clrq_relaxed(&ptr->pic.p_int_addr[int_n], in pcireg_intr_addr_addr_set()
183 __sn_setq_relaxed(&ptr->pic.p_int_addr[int_n], in pcireg_intr_addr_addr_set()
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | integratorap.dts | 150 pic: pic@14000000 { label
161 interrupt-parent = <&pic>;
178 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
179 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
180 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
181 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
183 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
184 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
185 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
186 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/ |
| D | mpc8272ads.dts | 69 compatible = "fsl,mpc8272ads-pci-pic",
70 "fsl,pq2ads-pci-pic";
74 interrupt-parent = <&PIC>;
108 interrupt-parent = <&PIC>;
156 interrupt-parent = <&PIC>;
167 interrupt-parent = <&PIC>;
176 interrupt-parent = <&PIC>;
191 interrupt-parent = <&PIC>;
197 interrupt-parent = <&PIC>;
210 interrupt-parent = <&PIC>;
[all …]
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| D | tqm8xx.dts | 39 interrupt-parent = <&PIC>;
73 interrupt-parent = <&PIC>;
85 interrupt-parent = <&PIC>;
115 interrupt-parent = <&PIC>;
120 PIC: pic@0 { label
124 compatible = "fsl,mpc860-pic", "fsl,pq1-pic";
156 CPM_PIC: pic@930 {
161 interrupt-parent = <&PIC>;
163 compatible = "fsl,mpc860-cpm-pic",
164 "fsl,cpm1-pic";
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| /kernel/linux/linux-5.10/arch/xtensa/boot/dts/ |
| D | virt.dts | 8 interrupt-parent = <&pic>;
37 pic: pic { label
38 compatible = "cdns,xtensa-pic";
64 0x0000 0x0 0x0 0x1 &pic 0x0 0x1
65 0x0800 0x0 0x0 0x1 &pic 0x1 0x1
66 0x1000 0x0 0x0 0x1 &pic 0x2 0x1
67 0x1800 0x0 0x0 0x1 &pic 0x3 0x1
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| /kernel/linux/linux-4.19/arch/powerpc/boot/dts/ |
| D | mpc8272ads.dts | 73 compatible = "fsl,mpc8272ads-pci-pic",
74 "fsl,pq2ads-pci-pic";
78 interrupt-parent = <&PIC>;
112 interrupt-parent = <&PIC>;
160 interrupt-parent = <&PIC>;
171 interrupt-parent = <&PIC>;
180 interrupt-parent = <&PIC>;
195 interrupt-parent = <&PIC>;
201 interrupt-parent = <&PIC>;
214 interrupt-parent = <&PIC>;
[all …]
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