Searched +full:pin +full:- +full:settings (Results 1 – 25 of 907) sorted by relevance
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx-pinctrl.txt | 7 different PAD settings (like pull up, keeper, etc) the IOMUXC controls
8 also the PAD settings parameters.
10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 Freescale IMX pin configuration node is a node of a group of pins which can be
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
24 Required properties for pin configuration node:
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| D | atmel,at91-pinctrl.txt | 7 different PAD settings (like pull up, keeper, etc) the controller controls
8 also the PAD settings parameters.
10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 Atmel AT91 pin configuration node is a node of a group of pins which can be
16 of the pins in that group. The 'pins' selects the function mode(also named pin
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, multi drive, etc.
21 - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
22 or "atmel,sama5d3-pinctrl"
[all …]
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| D | pinctrl-bindings.txt | 3 Hardware modules that control pin multiplexing or configuration parameters
4 such as pull-up/down, tri-state, drive-strength etc are designated as pin
5 controllers. Each pin controller must be represented as a node in device tree,
8 Hardware modules whose signals are affected by pin configuration are
12 For a client device to operate correctly, certain pin controllers must
13 set up certain specific pin configurations. Some client devices need a
14 single static pin configuration, e.g. set up during initialization. Others
15 need to reconfigure pins at run-time, for example to tri-state pins when the
21 for client device device tree nodes to map those state names to the pin
24 Note that pin controllers themselves may also be client devices of themselves.
[all …]
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| D | fsl,imx7d-pinctrl.txt | 3 iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar
4 as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
5 power state retention capabilities on gpios that are part of iomuxc-lpsr
6 (GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for
7 mux and pad control settings, it shares the input select register from main
8 iomuxc controller for daisy chain settings, the fsl,input-sel property extends
9 fsl,imx-pinctrl driver to support iomuxc-lpsr controller.
11 iomuxc_lpsr: iomuxc-lpsr@302c0000 {
12 compatible = "fsl,imx7d-iomuxc-lpsr";
14 fsl,input-sel = <&iomuxc>;
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx-pinctrl.txt | 7 different PAD settings (like pull up, keeper, etc) the IOMUXC controls
8 also the PAD settings parameters.
10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 Freescale IMX pin configuration node is a node of a group of pins which can be
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
24 Required properties for pin configuration node:
[all …]
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| D | atmel,at91-pinctrl.txt | 7 different PAD settings (like pull up, keeper, etc) the controller controls
8 also the PAD settings parameters.
10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 Atmel AT91 pin configuration node is a node of a group of pins which can be
16 of the pins in that group. The 'pins' selects the function mode(also named pin
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, multi drive, etc.
21 - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
22 or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
[all …]
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| D | pinmux-node.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic pin multiplexing node schema
10 - Linus Walleij <linus.walleij@linaro.org>
13 The contents of the pin configuration child nodes are defined by the binding
14 for the individual pin controller device. The pin configuration nodes need not
15 be direct children of the pin controller device; they may be grandchildren,
18 the binding for the individual pin controller device.
[all …]
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| D | fsl,imx7d-pinctrl.txt | 3 iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar
4 as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
5 power state retention capabilities on gpios that are part of iomuxc-lpsr
6 (GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for
7 mux and pad control settings, it shares the input select register from main
8 iomuxc controller for daisy chain settings, the fsl,input-sel property extends
9 fsl,imx-pinctrl driver to support iomuxc-lpsr controller.
11 iomuxc_lpsr: iomuxc-lpsr@302c0000 {
12 compatible = "fsl,imx7d-iomuxc-lpsr";
14 fsl,input-sel = <&iomuxc>;
[all …]
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| /kernel/linux/linux-4.19/Documentation/arm/pxa/ |
| D | mfp.txt | 5 MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
12 Unlike the GPIO alternate function settings on PXA25x and PXA27x, a new MFP
13 mechanism is introduced from PXA3xx to completely move the pin-mux functions
14 out of the GPIO controller. In addition to pin-mux configurations, the MFP
15 also controls the low power state, driving strength, pull-up/down and event
16 detection of each pin. Below is a diagram of internal connections between
19 +--------+
20 | |--(GPIO19)--+
22 | |--(GPIO...) |
23 +--------+ |
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/mvebu/ |
| D | pinctrl-mvebu.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * struct mvebu_mpp_ctrl_data - private data for the mpp ctrl operations
29 * struct mvebu_mpp_ctrl - describe a mpp control
31 * @pid: first pin id handled by this control
38 * A mpp_ctrl describes a muxable unit, e.g. pin, group of pins, or
40 * between two or more different settings, e.g. assign mpp pin 13 to
45 * to allow pin settings with varying gpio pins.
62 * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
64 * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
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| /kernel/linux/linux-4.19/drivers/pinctrl/mvebu/ |
| D | pinctrl-mvebu.h | 5 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
17 * struct mvebu_mpp_ctrl_data - private data for the mpp ctrl operations
33 * struct mvebu_mpp_ctrl - describe a mpp control
35 * @pid: first pin id handled by this control
42 * A mpp_ctrl describes a muxable unit, e.g. pin, group of pins, or
44 * between two or more different settings, e.g. assign mpp pin 13 to
49 * to allow pin settings with varying gpio pins.
66 * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
68 * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
73 * A ctrl_setting describes a specific internal mux function that a mpp pin
[all …]
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| /kernel/linux/linux-5.10/Documentation/arm/pxa/ |
| D | mfp.rst | 7 MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
14 Unlike the GPIO alternate function settings on PXA25x and PXA27x, a new MFP
15 mechanism is introduced from PXA3xx to completely move the pin-mux functions
16 out of the GPIO controller. In addition to pin-mux configurations, the MFP
17 also controls the low power state, driving strength, pull-up/down and event
18 detection of each pin. Below is a diagram of internal connections between
21 +--------+
22 | |--(GPIO19)--+
24 | |--(GPIO...) |
25 +--------+ |
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/ |
| D | core.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Core private header for the pin control subsystem
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
13 #include <linux/radix-tree.h>
20 * struct pinctrl_dev - pin control class device
21 * @node: node to include this pin controller in the global pin controller list
22 * @desc: the pin controller descriptor supplied when initializing this pin
24 * @pin_desc_tree: each pin descriptor for this pin controller is stored in
26 * @pin_group_tree: optionally each pin group can be stored in this radix tree
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| D | pinctrl-single.c | 2 * Generic device tree based pinctrl driver for one register per pin
29 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/platform_data/pinctrl-single.h>
38 #define DRIVER_NAME "pinctrl-single"
42 * struct pcs_func_vals - mux function register offset and value pair
54 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
71 * struct pcs_conf_type - pinconf property name, pinconf param pair
81 * struct pcs_function - pinctrl function
87 * @conf: array of pin configurations
88 * @nconfs: number of pin configurations available
[all …]
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| /kernel/linux/linux-4.19/drivers/pinctrl/ |
| D | core.h | 2 * Core private header for the pin control subsystem
4 * Copyright (C) 2011 ST-Ericsson SA
5 * Written on behalf of Linaro for ST-Ericsson
14 #include <linux/radix-tree.h>
21 * struct pinctrl_dev - pin control class device
22 * @node: node to include this pin controller in the global pin controller list
23 * @desc: the pin controller descriptor supplied when initializing this pin
25 * @pin_desc_tree: each pin descriptor for this pin controller is stored in
27 * @pin_group_tree: optionally each pin group can be stored in this radix tree
31 * @gpio_ranges: a list of GPIO ranges that is handled by this pin controller,
[all …]
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| /kernel/linux/linux-5.10/include/linux/ssb/ |
| D | ssb_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define SSB_MAX_NR_CORES ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
108 #define SSB_TMSHIGH_SERR 0x00000001 /* S-error */
168 * in two-byte quantities.
192 #define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
202 #define SSB_SPROM1_BINF_ANTBG 0x3000 /* Available B-PHY and G-PHY antennas */
204 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
210 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
211 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
214 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
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| /kernel/linux/linux-4.19/include/linux/ssb/ |
| D | ssb_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define SSB_MAX_NR_CORES ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
108 #define SSB_TMSHIGH_SERR 0x00000001 /* S-error */
168 * in two-byte quantities.
192 #define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
202 #define SSB_SPROM1_BINF_ANTBG 0x3000 /* Available B-PHY and G-PHY antennas */
204 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
210 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
211 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
214 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-s3c/ |
| D | gpio-cfg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
8 * S3C Platform - GPIO pin configuration
12 * pin configuration done such as setting a pin to input or output or
13 * changing the pull-{up,down} configurations.
27 /* forward declaration if gpio-core.h hasn't been included */
41 * per-bank configuration information that other systems such as the
64 /* Defines for generic pin configurations */
73 * s3c_gpio_cfgpin() - Change the GPIO function of a pin.
74 * @pin pin The pin number to configure.
75 * @to to The configuration for the pin's function.
[all …]
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| /kernel/linux/linux-4.19/arch/arm/plat-samsung/include/plat/ |
| D | gpio-cfg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
8 * S3C Platform - GPIO pin configuration
12 * pin configuration done such as setting a pin to input or output or
13 * changing the pull-{up,down} configurations.
27 /* forward declaration if gpio-core.h hasn't been included */
41 * per-bank configuration information that other systems such as the
64 /* Defines for generic pin configurations */
73 * s3c_gpio_cfgpin() - Change the GPIO function of a pin.
74 * @pin pin The pin number to configure.
75 * @to to The configuration for the pin's function.
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/tilcdc/ |
| D | panel.txt | 1 Device-Tree bindings for tilcdc DRM generic panel output driver
4 - compatible: value should be "ti,tilcdc,panel".
5 - panel-info: configuration info to configure LCDC correctly for the panel
6 - ac-bias: AC Bias Pin Frequency
7 - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt
8 - dma-burst-sz: DMA burst size
9 - bpp: Bits per pixel
10 - fdd: FIFO DMA Request Delay
11 - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
12 - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/tilcdc/ |
| D | panel.txt | 1 Device-Tree bindings for tilcdc DRM generic panel output driver
4 - compatible: value should be "ti,tilcdc,panel".
5 - panel-info: configuration info to configure LCDC correctly for the panel
6 - ac-bias: AC Bias Pin Frequency
7 - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt
8 - dma-burst-sz: DMA burst size
9 - bpp: Bits per pixel
10 - fdd: FIFO DMA Request Delay
11 - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
12 - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/inc/ |
| D | smu9_driver_if.h | 46 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
47 #define MAX_UVD_DPM_LEVEL (NUM_UVD_DPM_LEVELS - 1)
48 #define MAX_VCE_DPM_LEVEL (NUM_VCE_DPM_LEVELS - 1)
49 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
50 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
51 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
52 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
53 #define MAX_LINK_DPM_LEVEL (NUM_LINK_LEVELS - 1)
65 #define MAX_EVV_VOLTAGE_LEVEL (NUM_EVV_VOLTAGE_LEVELS - 1)
141 /* External Component Communication Settings */
[all …]
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| /kernel/linux/linux-4.19/drivers/gpu/drm/amd/powerplay/inc/ |
| D | smu9_driver_if.h | 46 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
47 #define MAX_UVD_DPM_LEVEL (NUM_UVD_DPM_LEVELS - 1)
48 #define MAX_VCE_DPM_LEVEL (NUM_VCE_DPM_LEVELS - 1)
49 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
50 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
51 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
52 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
53 #define MAX_LINK_DPM_LEVEL (NUM_LINK_LEVELS - 1)
65 #define MAX_EVV_VOLTAGE_LEVEL (NUM_EVV_VOLTAGE_LEVELS - 1)
141 /* External Component Communication Settings */
[all …]
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| /kernel/linux/linux-4.19/Documentation/driver-api/ |
| D | pinctl.rst | 2 PINCTRL (PIN CONTROL) subsystem
5 This document outlines the pin control subsystem in Linux
9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up/down, open drain,
17 Top-level interface
20 Definition of PIN CONTROLLER:
22 - A pin controller is a piece of hardware, usually a set of registers, that
26 Definition of PIN:
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| /kernel/linux/linux-5.10/Documentation/driver-api/ |
| D | pinctl.rst | 2 PINCTRL (PIN CONTROL) subsystem
5 This document outlines the pin control subsystem in Linux
9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up/down, open drain,
17 Top-level interface
20 Definition of PIN CONTROLLER:
22 - A pin controller is a piece of hardware, usually a set of registers, that
26 Definition of PIN:
[all …]
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