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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
12 (PLIC) high-level specification in the RISC-V Privileged Architecture
13 specification. The PLIC connects all external interrupts in the system to all
17 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
20 Each interrupt can be enabled on per-context basis. Any context can claim
[all …]
Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
21 entry, though external interrupt controllers (like the PLIC, for example) will
23 a PLIC interrupt property will typically list the HLICs for all present HARTs
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/
Dsifive,plic-1.0.0.txt1 SiFive Platform-Level Interrupt Controller (PLIC)
2 -------------------------------------------------
4 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
5 (PLIC) high-level specification in the RISC-V Privileged Architecture
6 specification. The PLIC connects all external interrupts in the system to all
10 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
13 Each interrupt can be enabled on per-context basis. Any context can claim
18 with priority below this threshold will not cause the PLIC to raise its
21 While the PLIC supports both edge-triggered and level-triggered interrupts,
23 specified in the PLIC device-tree binding.
[all …]
Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
21 entry, though external interrupt controllers (like the PLIC, for example) will
23 a PLIC interrupt property will typically list the HLICs for all present HARTs
[all …]
/kernel/linux/linux-4.19/drivers/irqchip/
Dirq-sifive-plic.c1 // SPDX-License-Identifier: GPL-2.0
6 #define pr_fmt(fmt) "plic: " fmt
20 * This driver implements a version of the RISC-V PLIC with the actual layout
23 * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
25 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
26 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
84 u32 hwirq_mask = 1 << (hwirq % 32); in plic_toggle()
98 writel(enable, plic_regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); in plic_irq_toggle()
102 if (handler->present) in plic_irq_toggle()
103 plic_toggle(handler->ctxid, d->hwirq, enable); in plic_irq_toggle()
[all …]
DKconfig23 default 1
192 bool "J-Core integrated AIC" if COMPILE_TEST
196 Support for the J-Core integrated AIC.
225 tristate "TS-4800 IRQ controller"
230 Support for the TS-4800 FPGA IRQ controller
375 bool "SiFive Platform-Level Interrupt Controller"
378 This enables support for the PLIC chip found in SiFive (and
379 potentially other) RISC-V systems. The PLIC controls devices
382 interrupt sources are subordinate to the PLIC.
/kernel/linux/linux-5.10/drivers/irqchip/
Dirq-sifive-plic.c1 // SPDX-License-Identifier: GPL-2.0
6 #define pr_fmt(fmt) "plic: " fmt
23 * This driver implements a version of the RISC-V PLIC with the actual layout
26 * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
28 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
29 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
87 u32 __iomem *reg = handler->enable_base + (hwirq / 32) * sizeof(u32); in plic_toggle()
88 u32 hwirq_mask = 1 << (hwirq % 32); in plic_toggle()
90 raw_spin_lock(&handler->enable_lock); in plic_toggle()
95 raw_spin_unlock(&handler->enable_lock); in plic_toggle()
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
23 default 1
216 bool "J-Core integrated AIC" if COMPILE_TEST
220 Support for the J-Core integrated AIC.
231 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
234 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
239 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
274 tristate "TS-4800 IRQ controller"
279 Support for the TS-4800 FPGA IRQ controller
443 bool "C-SKY Multi Processor Interrupt Controller"
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpio/
Dsifive,gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yash Shah <yash.shah@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
16 - const: sifive,fu540-c000-gpio
17 - const: sifive,gpio0
20 maxItems: 1
25 minItems: 1
28 interrupt-controller: true
[all …]
/kernel/linux/linux-5.10/arch/m68k/include/asm/
Dm5272sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5272sim.h -- ColdFire 5272 System Integration Module support.
31 #define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */
68 #define MCFSIM_DCAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address */
69 #define MCFSIM_DCMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg */
70 #define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */
100 #define MCF_IRQ_EINT1 65 /* External Interrupt 1 */
104 #define MCF_IRQ_TIMER1 69 /* Timer 1 */
109 #define MCF_IRQ_UART1 74 /* UART 1 */
110 #define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
[all …]
/kernel/linux/linux-4.19/arch/m68k/include/asm/
Dm5272sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5272sim.h -- ColdFire 5272 System Integration Module support.
31 #define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */
68 #define MCFSIM_DCAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address */
69 #define MCFSIM_DCMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg */
70 #define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */
100 #define MCF_IRQ_EINT1 65 /* External Interrupt 1 */
104 #define MCF_IRQ_TIMER1 69 /* Timer 1 */
109 #define MCF_IRQ_UART1 74 /* UART 1 */
110 #define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pwm/
Dpwm-sifive.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yash Shah <yash.shah@sifive.com>
12 - Sagar Kadam <sagar.kadam@sifive.com>
13 - Paul Walmsley <paul.walmsley@sifive.com>
21 numbers can be found here -
23 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
28 - const: sifive,fu540-c000-pwm
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/
Dspi-sifive.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: "spi-controller.yaml#"
20 - const: sifive,fu540-c000-spi
21 - const: sifive,spi0
[all …]
/kernel/linux/linux-5.10/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
[all …]