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/kernel/linux/linux-4.19/arch/powerpc/boot/dts/fsl/
Dqoriq-clockgen1.dtsi49 pll0: pll0@800 { label
54 clock-output-names = "pll0", "pll0-div2";
67 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
68 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
75 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
76 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dqoriq-clockgen2.dtsi48 pll0: pll0@800 { label
53 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
Dt1040si-post.dtsi433 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
435 clock-names = "pll0", "pll0-div2", "pll1-div4",
444 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
446 clock-names = "pll0", "pll0-div2", "pll1-div4",
455 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
457 clock-names = "pll0", "pll0-div2", "pll1-div4",
466 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
Dt2081si-post.dtsi543 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
545 clock-names = "pll0", "pll0-div2", "pll0-div4",
554 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
556 clock-names = "pll0", "pll0-div2", "pll0-div4",
Dp2041si-post.dtsi335 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
336 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
344 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
345 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dp5040si-post.dtsi327 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
328 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
336 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
337 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dp3041si-post.dtsi362 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
363 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
371 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
372 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ti/davinci/
Dpll.txt9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
20 This property is only valid when compatible = "ti,da850-pll0".
42 This child node is only valid when compatible = "ti,da850-pll0".
56 pll0: clock-controller@11000 {
57 compatible = "ti,da850-pll0";
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/ti/davinci/
Dpll.txt9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
20 This property is only valid when compatible = "ti,da850-pll0".
42 This child node is only valid when compatible = "ti,da850-pll0".
56 pll0: clock-controller@11000 {
57 compatible = "ti,da850-pll0";
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/
Dqoriq-clock.txt152 pll0: pll0@800 {
157 clock-output-names = "pll0", "pll0-div2";
172 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
173 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
181 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
182 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Drenesas,r8a73a4-cpg-clocks.txt17 "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
29 clock-output-names = "main", "pll0", "pll1", "pll2",
Drenesas,sh73a0-cpg-clocks.txt19 "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
31 clock-output-names = "main", "pll0", "pll1", "pll2",
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dqoriq-clock.txt159 pll0: pll0@800 {
164 clock-output-names = "pll0", "pll0-div2";
179 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
180 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
188 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
189 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
/kernel/linux/linux-5.10/drivers/clk/mxs/
Dclk-imx28.c127 static const char *const sel_pll0[] __initconst = { "pll0", "ref_xtal", };
130 static const char *const ptp_sels[] __initconst = { "ref_xtal", "pll0", };
133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
168 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
171 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); in mx28_clocks_init()
172 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); in mx28_clocks_init()
173 clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); in mx28_clocks_init()
174 clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); in mx28_clocks_init()
175 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0); in mx28_clocks_init()
176 clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1); in mx28_clocks_init()
[all …]
/kernel/linux/linux-4.19/drivers/clk/mxs/
Dclk-imx28.c133 static const char *const sel_pll0[] __initconst = { "pll0", "ref_xtal", };
136 static const char *const ptp_sels[] __initconst = { "ref_xtal", "pll0", };
139 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
174 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
177 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); in mx28_clocks_init()
178 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); in mx28_clocks_init()
179 clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); in mx28_clocks_init()
180 clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); in mx28_clocks_init()
181 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0); in mx28_clocks_init()
182 clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1); in mx28_clocks_init()
[all …]
/kernel/linux/linux-5.10/drivers/clk/mvebu/
Dcp110-system-controller.c14 * - PLL0 (1 Ghz)
15 * - PPv2 core (1/3 PLL0)
16 * - x2 Core (1/2 PLL0)
18 * - SDIO (2/5 PLL0)
22 * - 2/5 PLL0
247 /* Register the PLL0 which is the root of the hw tree */ in cp110_syscon_common_probe()
248 pll0_name = ap_cp_unique_name(dev, syscon_node, "pll0"); in cp110_syscon_common_probe()
258 /* PPv2 is PLL0/3 */ in cp110_syscon_common_probe()
268 /* X2CORE clock is PLL0/2 */ in cp110_syscon_common_probe()
289 /* NAND can be either PLL0/2.5 or core clock */ in cp110_syscon_common_probe()
[all …]
/kernel/linux/linux-4.19/drivers/bcma/
Ddriver_chipcommon_pmu.c84 u32 pll0, mask; in bcma_pmu2_pll_init0() local
115 pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0); in bcma_pmu2_pll_init0()
116 freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >> in bcma_pmu2_pll_init0()
137 pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK; in bcma_pmu2_pll_init0()
138 pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT; in bcma_pmu2_pll_init0()
139 bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0); in bcma_pmu2_pll_init0()
347 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
349 static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) in bcma_pmu_pll_clock() argument
354 BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0)); in bcma_pmu_pll_clock()
366 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF); in bcma_pmu_pll_clock()
[all …]
/kernel/linux/linux-5.10/drivers/bcma/
Ddriver_chipcommon_pmu.c84 u32 pll0, mask; in bcma_pmu2_pll_init0() local
115 pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0); in bcma_pmu2_pll_init0()
116 freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >> in bcma_pmu2_pll_init0()
137 pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK; in bcma_pmu2_pll_init0()
138 pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT; in bcma_pmu2_pll_init0()
139 bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0); in bcma_pmu2_pll_init0()
351 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
353 static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) in bcma_pmu_pll_clock() argument
358 BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0)); in bcma_pmu_pll_clock()
370 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF); in bcma_pmu_pll_clock()
[all …]
/kernel/linux/linux-4.19/drivers/clk/mvebu/
Dcp110-system-controller.c16 * - PLL0 (1 Ghz)
17 * - PPv2 core (1/3 PLL0)
18 * - x2 Core (1/2 PLL0)
20 * - SDIO (2/5 PLL0)
24 * - 2/5 PLL0
265 /* Register the PLL0 which is the root of the hw tree */ in cp110_syscon_common_probe()
266 pll0_name = cp110_unique_name(dev, syscon_node, "pll0"); in cp110_syscon_common_probe()
276 /* PPv2 is PLL0/3 */ in cp110_syscon_common_probe()
286 /* X2CORE clock is PLL0/2 */ in cp110_syscon_common_probe()
307 /* NAND can be either PLL0/2.5 or core clock */ in cp110_syscon_common_probe()
[all …]
/kernel/linux/linux-5.10/drivers/soc/kendryte/
Dk210-sysctl.c136 u32 clksel0, pll0; in k210_sysctl_clk_recalc_rate() local
141 * Otherwise, use PLL0 frequency with a frequency divisor. in k210_sysctl_clk_recalc_rate()
148 * Get PLL0 frequency: in k210_sysctl_clk_recalc_rate()
151 pll0 = readl(s->regs + K210_SYSCTL_PLL0); in k210_sysctl_clk_recalc_rate()
152 clkr0 = 1 + FIELD_GET(GENMASK(3, 0), pll0); in k210_sysctl_clk_recalc_rate()
153 clkf0 = 1 + FIELD_GET(GENMASK(9, 4), pll0); in k210_sysctl_clk_recalc_rate()
154 clkod0 = 1 + FIELD_GET(GENMASK(13, 10), pll0); in k210_sysctl_clk_recalc_rate()
/kernel/linux/linux-5.10/include/linux/firmware/imx/svc/
Dpm.h80 #define IMX_SC_PM_PARENT_PLL0 1 /* Parent is PLL0 */
81 #define IMX_SC_PM_PARENT_PLL1 2 /* Parent is PLL1 or PLL0/2 */
82 #define IMX_SC_PM_PARENT_PLL2 3 /* Parent in PLL2 or PLL0/4 */
/kernel/linux/linux-4.19/arch/arm/mach-w90x900/
Dclksel.c27 #define PLL0 0x00 macro
77 if (strcmp(src, "pll0") == 0) in nuc900_clock_source()
78 clkval = PLL0; in nuc900_clock_source()
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dstih407-clock.dtsi80 compatible = "st,clkgen-pll0";
119 clk_s_c0_pll0: clk-s-c0-pll0 {
121 compatible = "st,clkgen-pll0";
125 clock-output-names = "clk-s-c0-pll0-odf-0";
126 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dstih407-clock.dtsi77 compatible = "st,clkgen-pll0";
116 clk_s_c0_pll0: clk-s-c0-pll0 {
118 compatible = "st,clkgen-pll0";
122 clock-output-names = "clk-s-c0-pll0-odf-0";
123 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
Dstih410-clock.dtsi77 compatible = "st,clkgen-pll0";
117 clk_s_c0_pll0: clk-s-c0-pll0 {
119 compatible = "st,clkgen-pll0";
123 clock-output-names = "clk-s-c0-pll0-odf-0";
124 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */

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