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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dallwinner,sun4i-a10-pll1-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll1-clk.yaml#
21 - allwinner,sun4i-a10-pll1-clk
22 - allwinner,sun6i-a31-pll1-clk
23 - allwinner,sun8i-a23-pll1-clk
47 compatible = "allwinner,sun4i-a10-pll1";
56 compatible = "allwinner,sun6i-a31-pll1-clk";
59 clock-output-names = "pll1";
65 compatible = "allwinner,sun8i-a23-pll1-clk";
68 clock-output-names = "pll1";
Dqoriq-clock.txt167 pll1: pll1@820 {
172 clock-output-names = "pll1", "pll1-div2";
179 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
180 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
188 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
189 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
/kernel/linux/linux-4.19/arch/powerpc/boot/dts/fsl/
Dqoriq-clockgen1.dtsi56 pll1: pll1@820 { label
61 clock-output-names = "pll1", "pll1-div2";
67 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
68 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
75 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
76 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dt1040si-post.dtsi434 <&pll1 0>, <&pll1 1>, <&pll1 2>;
435 clock-names = "pll0", "pll0-div2", "pll1-div4",
436 "pll1", "pll1-div2", "pll1-div4";
445 <&pll1 0>, <&pll1 1>, <&pll1 2>;
446 clock-names = "pll0", "pll0-div2", "pll1-div4",
447 "pll1", "pll1-div2", "pll1-div4";
456 <&pll1 0>, <&pll1 1>, <&pll1 2>;
457 clock-names = "pll0", "pll0-div2", "pll1-div4",
458 "pll1", "pll1-div2", "pll1-div4";
467 <&pll1 0>, <&pll1 1>, <&pll1 2>;
Dqoriq-clockgen2.dtsi55 pll1: pll1@820 { label
60 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
Dt2081si-post.dtsi544 <&pll1 0>, <&pll1 1>, <&pll1 2>;
546 "pll1", "pll1-div2", "pll1-div4";
555 <&pll1 0>, <&pll1 1>, <&pll1 2>;
557 "pll1", "pll1-div2", "pll1-div4";
Dp2041si-post.dtsi335 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
336 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
344 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
345 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dp5040si-post.dtsi327 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
328 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
336 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
337 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/
Dqoriq-clock.txt160 pll1: pll1@820 {
165 clock-output-names = "pll1", "pll1-div2";
172 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
173 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
181 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
182 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dsunxi.txt10 "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
148 pll1: clk@1c20000 {
150 compatible = "allwinner,sun4i-a10-pll1-clk";
153 clock-output-names = "pll1";
176 clocks = <&osc32k>, <&osc24M>, <&pll1>;
/kernel/linux/linux-5.10/include/linux/iio/frequency/
Dad9523.h117 * @refa_r_div: PLL1 10-bit REFA R divider.
118 * @refb_r_div: PLL1 10-bit REFB R divider.
119 * @pll1_feedback_div: PLL1 10-bit Feedback N divider.
120 * @pll1_charge_pump_current_nA: Magnitude of PLL1 charge pump current (nA).
122 * @osc_in_feedback_en: PLL1 feedback path, local feedback from
124 * @pll1_loop_filter_rzero: PLL1 Loop Filter Zero Resistor selection.
160 /* PLL1 Setting */
/kernel/linux/linux-4.19/include/linux/iio/frequency/
Dad9523.h118 * @refa_r_div: PLL1 10-bit REFA R divider.
119 * @refb_r_div: PLL1 10-bit REFB R divider.
120 * @pll1_feedback_div: PLL1 10-bit Feedback N divider.
121 * @pll1_charge_pump_current_nA: Magnitude of PLL1 charge pump current (nA).
123 * @osc_in_feedback_en: PLL1 feedback path, local feedback from
125 * @pll1_loop_filter_rzero: PLL1 Loop Filter Zero Resistor selection.
161 /* PLL1 Setting */
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ti/davinci/
Dpll.txt10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
15 - for "ti,da850-pll1", shall be "clksrc"
80 pll1: clock-controller@21a000 {
81 compatible = "ti,da850-pll1";
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/ti/davinci/
Dpll.txt10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
15 - for "ti,da850-pll1", shall be "clksrc"
80 pll1: clock-controller@21a000 {
81 compatible = "ti,da850-pll1";
/kernel/linux/linux-4.19/drivers/clk/renesas/
Dclk-sh73a0.c51 { "m3", "pll1", CPG_FRQCRA, 12 },
52 { "b", "pll1", CPG_FRQCRA, 8 },
53 { "m1", "pll1", CPG_FRQCRA, 4 },
54 { "m2", "pll1", CPG_FRQCRA, 0 },
55 { "zx", "pll1", CPG_FRQCRB, 12 },
56 { "hp", "pll1", CPG_FRQCRB, 4 },
115 /* handle CFG bit for PLL1 and PLL2 */ in sh73a0_cpg_register_clock()
Dclk-rcar-gen2.c118 * Since this value might be dependent on external xtal rate, pll1 in cpg_z_clk_set_rate()
212 const char *parent_name = "pll1"; in cpg_adsp_clk_register()
253 * MD EXTAL PLL0 PLL1 PLL3
338 } else if (!strcmp(name, "pll1")) { in rcar_gen2_cpg_register_clock()
345 parent_name = "pll1"; in rcar_gen2_cpg_register_clock()
352 parent_name = "pll1"; in rcar_gen2_cpg_register_clock()
356 parent_name = "pll1"; in rcar_gen2_cpg_register_clock()
360 parent_name = "pll1"; in rcar_gen2_cpg_register_clock()
/kernel/linux/linux-5.10/drivers/clk/renesas/
Dclk-sh73a0.c49 { "m3", "pll1", CPG_FRQCRA, 12 },
50 { "b", "pll1", CPG_FRQCRA, 8 },
51 { "m1", "pll1", CPG_FRQCRA, 4 },
52 { "m2", "pll1", CPG_FRQCRA, 0 },
53 { "zx", "pll1", CPG_FRQCRB, 12 },
54 { "hp", "pll1", CPG_FRQCRB, 4 },
113 /* handle CFG bit for PLL1 and PLL2 */ in sh73a0_cpg_register_clock()
/kernel/linux/linux-5.10/drivers/clk/mmp/
Dclk-pxa910.c107 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000); in pxa910_clk_init()
108 clk_register_clkdev(clk, "pll1", NULL); in pxa910_clk_init()
110 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", in pxa910_clk_init()
146 clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1", in pxa910_clk_init()
150 clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1", in pxa910_clk_init()
154 clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1", in pxa910_clk_init()
158 clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1", in pxa910_clk_init()
Dclk-pxa168.c102 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000); in pxa168_clk_init()
103 clk_register_clkdev(clk, "pll1", NULL); in pxa168_clk_init()
105 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", in pxa168_clk_init()
141 clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1", in pxa168_clk_init()
145 clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1", in pxa168_clk_init()
149 clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1", in pxa168_clk_init()
153 clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1", in pxa168_clk_init()
/kernel/linux/linux-4.19/drivers/clk/mmp/
Dclk-pxa910.c106 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000); in pxa910_clk_init()
107 clk_register_clkdev(clk, "pll1", NULL); in pxa910_clk_init()
109 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", in pxa910_clk_init()
145 clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1", in pxa910_clk_init()
149 clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1", in pxa910_clk_init()
153 clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1", in pxa910_clk_init()
157 clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1", in pxa910_clk_init()
Dclk-pxa168.c101 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000); in pxa168_clk_init()
102 clk_register_clkdev(clk, "pll1", NULL); in pxa168_clk_init()
104 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", in pxa168_clk_init()
140 clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1", in pxa168_clk_init()
144 clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1", in pxa168_clk_init()
148 clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1", in pxa168_clk_init()
152 clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1", in pxa168_clk_init()
/kernel/liteos_m/targets/riscv_nuclei_gd32vf103_soc_gcc/SoC/gd32vf103/Common/Include/
Dgd32vf103_rcu.h72 #define RCU_CTL_PLL1EN BIT(26) /*!< PLL1 enable */
73 #define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization fla…
98 #define RCU_INT_PLL1STBIF BIT(5) /*!< PLL1 stabilization interrupt…
106 #define RCU_INT_PLL1STBIE BIT(13) /*!< PLL1 stabilization interrupt…
113 #define RCU_INT_PLL1STBIC BIT(21) /*!< PLL1 stabilization interrupt…
222 #define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication fa…
396 RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLL1 stabilization flags */
416 …RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLL1 stabilization interrupt fl…
428 …RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLL1 stabilization interrup…
440 RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-w90x900/
Dclksel.c28 #define PLL1 0x01 macro
79 else if (strcmp(src, "pll1") == 0) in nuc900_clock_source()
80 clkval = PLL1; in nuc900_clock_source()
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv04.c207 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_double_highregs() local
214 /* model specific additions to generic pll1 and pll2 set up above */ in setPLL_double_highregs()
216 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | in setPLL_double_highregs()
231 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()
/kernel/linux/linux-4.19/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv04.c207 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_double_highregs() local
214 /* model specific additions to generic pll1 and pll2 set up above */ in setPLL_double_highregs()
216 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | in setPLL_double_highregs()
231 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()

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