| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun9i-a80-pll4-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-pll4-clk.yaml#
20 const: allwinner,sun9i-a80-pll4-clk
44 compatible = "allwinner,sun9i-a80-pll4-clk";
47 clock-output-names = "pll4";
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| D | allwinner,sun9i-a80-apb0-clk.yaml | 50 clocks = <&osc24M>, <&pll4>;
59 clocks = <&osc24M>, <&pll4>;
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| D | allwinner,sun4i-a10-ve-clk.yaml | 51 clocks = <&pll4>;
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| D | allwinner,sun9i-a80-ahb-clk.yaml | 48 clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
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| D | allwinner,sun9i-a80-cpus-clk.yaml | 48 clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
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| D | allwinner,sun9i-a80-gt-clk.yaml | 48 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
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| /kernel/linux/linux-4.19/drivers/clk/qcom/ |
| D | lcc-ipq806x.c | 34 static struct clk_pll pll4 = { variable
43 .name = "pll4",
402 [PLL4] = &pll4.clkr,
445 /* Configure the rate of PLL4 if the bootloader hasn't already */ in lcc_ipq806x_probe()
448 clk_pll_configure_sr(&pll4, regmap, &pll4_config, true); in lcc_ipq806x_probe()
449 /* Enable PLL4 source on the LPASS Primary PLL Mux */ in lcc_ipq806x_probe()
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| D | lcc-msm8960.c | 34 static struct clk_pll pll4 = { variable
43 .name = "pll4",
487 [PLL4] = &pll4.clkr,
551 /* Use the correct frequency plan depending on speed of PLL4 */ in lcc_msm8960_probe()
562 /* Enable PLL4 source on the LPASS Primary PLL Mux */ in lcc_msm8960_probe()
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| D | lcc-mdm9615.c | 36 static struct clk_pll pll4 = { variable
45 .name = "pll4",
489 [PLL4] = &pll4.clkr,
552 /* Use the correct frequency plan depending on speed of PLL4 */ in lcc_mdm9615_probe()
563 /* Enable PLL4 source on the LPASS Primary PLL Mux */ in lcc_mdm9615_probe()
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| /kernel/linux/linux-5.10/drivers/clk/qcom/ |
| D | lcc-ipq806x.c | 26 static struct clk_pll pll4 = { variable
35 .name = "pll4",
394 [PLL4] = &pll4.clkr,
437 /* Configure the rate of PLL4 if the bootloader hasn't already */ in lcc_ipq806x_probe()
440 clk_pll_configure_sr(&pll4, regmap, &pll4_config, true); in lcc_ipq806x_probe()
441 /* Enable PLL4 source on the LPASS Primary PLL Mux */ in lcc_ipq806x_probe()
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| D | lcc-msm8960.c | 26 static struct clk_pll pll4 = { variable
35 .name = "pll4",
479 [PLL4] = &pll4.clkr,
543 /* Use the correct frequency plan depending on speed of PLL4 */ in lcc_msm8960_probe()
554 /* Enable PLL4 source on the LPASS Primary PLL Mux */ in lcc_msm8960_probe()
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| D | lcc-mdm9615.c | 28 static struct clk_pll pll4 = { variable
37 .name = "pll4",
481 [PLL4] = &pll4.clkr,
544 /* Use the correct frequency plan depending on speed of PLL4 */ in lcc_mdm9615_probe()
555 /* Enable PLL4 source on the LPASS Primary PLL Mux */ in lcc_mdm9615_probe()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/ |
| D | ti,j721e-cpb-audio.yaml | 17 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
23 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
32 PLL4 ---> PLL4_HSDIV0 ---> MCASP0_AUXCLK ---> McASP0.auxclk
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| D | ti,j721e-cpb-ivi-audio.yaml | 22 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
26 Note: the same PLL4 and PLL15 is used by the audio support on the CPB!
29 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
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| /kernel/linux/linux-4.19/drivers/clk/sunxi/ |
| D | clk-sun9i-core.c | 27 * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
28 * PLL4 rate is calculated as follows
91 pr_err("Could not get registers for a80-pll4-clk: %s\n", in sun9i_a80_pll4_setup()
99 CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup);
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| D | clk-sun9i-cpus.c | 61 /* apply pre-divider first if parent is pll4 */ in sun9i_a80_cpus_clk_recalc_rate()
85 /* calculate pre-divider if parent is pll4 */ in sun9i_a80_cpus_clk_round()
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| /kernel/linux/linux-5.10/drivers/clk/sunxi/ |
| D | clk-sun9i-core.c | 18 * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
19 * PLL4 rate is calculated as follows
82 pr_err("Could not get registers for a80-pll4-clk: %pOFn\n", in sun9i_a80_pll4_setup()
90 CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup);
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| D | clk-sun9i-cpus.c | 62 /* apply pre-divider first if parent is pll4 */ in sun9i_a80_cpus_clk_recalc_rate()
86 /* calculate pre-divider if parent is pll4 */ in sun9i_a80_cpus_clk_round()
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| /kernel/linux/linux-4.19/arch/powerpc/boot/dts/fsl/ |
| D | t4240si-post.dtsi | 970 pll4: pll4@880 { label
975 clock-output-names = "pll4", "pll4-div2", "pll4-div4";
1009 <&pll4 0>, <&pll4 1>, <&pll4 2>;
1011 "pll4", "pll4-div2", "pll4-div4";
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| /kernel/linux/linux-5.10/include/dt-bindings/clock/ |
| D | qcom,lcc-ipq806x.h | 9 #define PLL4 0 macro
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| D | qcom,lcc-msm8960.h | 9 #define PLL4 0 macro
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| D | qcom,lcc-mdm9615.h | 11 #define PLL4 0 macro
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| /kernel/linux/linux-4.19/include/dt-bindings/clock/ |
| D | qcom,lcc-ipq806x.h | 17 #define PLL4 0 macro
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| D | qcom,lcc-msm8960.h | 17 #define PLL4 0 macro
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| D | qcom,lcc-mdm9615.h | 19 #define PLL4 0 macro
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