| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun4i-a10-pll5-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll5-clk.yaml#
23 const: allwinner,sun4i-a10-pll5-clk
47 compatible = "allwinner,sun4i-a10-pll5-clk";
|
| D | allwinner,sun4i-a10-mbus-clk.yaml | 50 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
59 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
|
| D | allwinner,sun4i-a10-display-clk.yaml | 53 clocks = <&pll3>, <&pll7>, <&pll5 1>;
|
| D | allwinner,sun4i-a10-mmc-clk.yaml | 71 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
| D | allwinner,sun4i-a10-mod0-clk.yaml | 67 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/ |
| D | sunxi.txt | 15 "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
98 "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",
156 pll5: clk@1c20020 {
158 compatible = "allwinner,sun4i-pll5-clk";
184 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
| /kernel/linux/linux-5.10/drivers/clk/renesas/ |
| D | r8a779a0-cpg-mssr.c | 101 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN),
231 * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC
243 /* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/ |
| D | simple-framebuffer-sunxi.txt | 33 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mips/ |
| D | mscc.txt | 48 configuration and status of PLL5, RCOMP, SyncE, SerDes configurations and
|
| /kernel/linux/linux-5.10/drivers/clk/mmp/ |
| D | clk-of-pxa1928.c | 41 {0, "pll5", NULL, 0, 1248000000},
146 static const char *sdh_parent_names[] = {"pll1_624", "pll5p", "pll5", "pll1_416"};
|
| /kernel/linux/linux-4.19/drivers/clk/mmp/ |
| D | clk-of-pxa1928.c | 41 {0, "pll5", NULL, 0, 1248000000},
147 static const char *sdh_parent_names[] = {"pll1_624", "pll5p", "pll5", "pll1_416"};
|
| /kernel/linux/linux-5.10/drivers/clk/sunxi/ |
| D | clk-sunxi.c | 195 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
196 * PLL5 rate is calculated as follows
1017 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT; in sunxi_divs_clk_setup()
1114 CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk",
|
| D | clk-factors.c | 195 * some factor clocks, such as pll5 and pll6, may have multiple in __sunxi_factors_register()
|
| /kernel/linux/linux-4.19/drivers/clk/sunxi/ |
| D | clk-sunxi.c | 203 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
204 * PLL5 rate is calculated as follows
1025 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT; in sunxi_divs_clk_setup()
1122 CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk",
|
| D | clk-factors.c | 198 * some factor clocks, such as pll5 and pll6, may have multiple in __sunxi_factors_register()
|
| /kernel/linux/linux-4.19/include/dt-bindings/clock/ |
| D | qcom,gcc-msm8660.h | 266 #define PLL5 249 macro
|
| D | qcom,gcc-mdm9615.h | 299 #define PLL5 281 macro
|
| D | qcom,gcc-msm8960.h | 297 #define PLL5 281 macro
|
| /kernel/linux/linux-5.10/include/dt-bindings/clock/ |
| D | qcom,gcc-msm8660.h | 258 #define PLL5 249 macro
|
| D | qcom,gcc-mdm9615.h | 291 #define PLL5 281 macro
|
| D | qcom,gcc-msm8960.h | 289 #define PLL5 281 macro
|
| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | clk-imx6sl.c | 67 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
220 hws[IMX6SL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); in imx6sl_clocks_init()
435 /* set PLL5 video as lcdif pix parent clock */ in imx6sl_clocks_init()
|
| /kernel/linux/linux-4.19/drivers/clk/imx/ |
| D | clk-imx6sl.c | 72 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
222 clks[IMX6SL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); in imx6sl_clocks_init()
438 /* set PLL5 video as lcdif pix parent clock */ in imx6sl_clocks_init()
|
| D | clk-imx6sll.c | 27 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
119 …clks[IMX6SLL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f… in imx6sll_clocks_init()
|
| D | clk-vf610.c | 85 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
227 clk[VF610_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll5", "pll5_bypass_src", PLL5_CTRL, 0x3); in vf610_clocks_init()
|