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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dkeystone-pll.txt1 Status: Unstable - ABI compatibility may be broken in the future
4 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
14 - #clock-cells : from common clock binding; shall be set to 0.
15 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
16 - clocks : parent clock phandle
17 - reg - pll control0 and pll multipler registers
18 - reg-names : control, multiplier and post-divider. The multiplier and
19 post-divider registers are applicable only for main pll clock
20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
[all …]
Dst,stm32-rcc.txt6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
16 - reg: should be register base and length as documented in the
18 - #reset-cells: 1, see below
19 - #clock-cells: 2, device nodes should specify the clock in their "clocks"
21 between gated clocks and other clocks and an index specifying the clock to
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/
Dkeystone-pll.txt1 Status: Unstable - ABI compatibility may be broken in the future
4 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
14 - #clock-cells : from common clock binding; shall be set to 0.
15 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
16 - clocks : parent clock phandle
17 - reg - pll control0 and pll multipler registers
18 - reg-names : control, multiplier and post-divider. The multiplier and
19 post-divider registers are applicable only for main pll clock
20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
[all …]
Dst,stm32-rcc.txt6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 - reg: should be register base and length as documented in the
16 - #reset-cells: 1, see below
17 - #clock-cells: 2, device nodes should specify the clock in their "clocks"
19 between gated clocks and other clocks and an index specifying the clock to
21 - clocks: External oscillator clock phandle
[all …]
/kernel/linux/linux-5.10/drivers/clk/ingenic/
Dcgu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2013-2015 Imagination Technologies
13 #include <linux/clk-provider.h>
18 * struct ingenic_cgu_pll_info - information about a PLL
33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
34 * the index of the lowest bit of the post-VCO divider value in
36 * @od_bits: the size of the post-VCO divider field in bits
37 * @od_max: the maximum post-VCO divider value
38 * @od_encoding: a pointer to an array mapping post-VCO divider values to
39 * their encoded values in the PLL control register, or -1 for
[all …]
/kernel/linux/linux-4.19/drivers/clk/ingenic/
Dcgu.h4 * Copyright (c) 2013-2015 Imagination Technologies
26 * struct ingenic_cgu_pll_info - information about a PLL
40 * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
41 * the index of the lowest bit of the post-VCO divider value in
43 * @od_bits: the size of the post-VCO divider field in bits
44 * @od_max: the maximum post-VCO divider value
45 * @od_encoding: a pointer to an array mapping post-VCO divider values to
46 * their encoded values in the PLL control register, or -1 for
66 * struct ingenic_cgu_mux_info - information about a clock mux
79 * struct ingenic_cgu_div_info - information about a divider
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/ata/
Dsata_highbank.txt3 SATA nodes are defined to describe on-chip Serial ATA controllers.
9 - compatible : compatible list, contains "calxeda,hb-ahci"
10 - interrupts : <interrupt mapping for SATA IRQ>
11 - reg : <registers mapping>
14 - dma-coherent : Present if dma operations are coherent
15 - calxeda,port-phys : phandle-combophy and lane assignment, which maps each
18 - calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off,
21 - calxeda,led-order : a u32 array that map port numbers to offsets within the
23 - calxeda,tx-atten : a u32 array that contains TX attenuation override
26 - calxeda,pre-clocks : a u32 that indicates the number of additional clock
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/ata/
Dsata_highbank.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Andre Przywara <andre.przywara@arm.com>
19 const: calxeda,hb-ahci
27 dma-coherent: true
29 calxeda,pre-clocks:
35 calxeda,post-clocks:
41 calxeda,led-order:
43 $ref: /schemas/types.yaml#/definitions/uint32-array
[all …]
/kernel/linux/linux-4.19/Documentation/gpu/
Dmeson.rst5 .. kernel-doc:: drivers/gpu/drm/meson/meson_drv.c
16 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
18 D |-------| |----| | | | | HDMI PLL |
19 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
20 R |-------| |----| Processing | | | | |
21 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
22 R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----|
23 A | osd1 | | | Blenders | | Encl ----------|----|---------------|
24 M |-------|______|----|____________| |________________| | |
30 .. kernel-doc:: drivers/gpu/drm/meson/meson_viu.c
[all …]
/kernel/linux/linux-5.10/Documentation/gpu/
Dmeson.rst5 .. kernel-doc:: drivers/gpu/drm/meson/meson_drv.c
16 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
18 D |-------| |----| | | | | HDMI PLL |
19 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
20 R |-------| |----| Processing | | | | |
21 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
22 R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----|
23 A | osd1 | | | Blenders | | Encl ----------|----|---------------|
24 M |-------|______|----|____________| |________________| | |
30 .. kernel-doc:: drivers/gpu/drm/meson/meson_viu.c
[all …]
/kernel/linux/linux-5.10/drivers/clk/samsung/
Dclk-cpu.c1 // SPDX-License-Identifier: GPL-2.0-only
13 * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
14 * clock for CPU domain. The rates of these auxiliary clocks are related to the
19 * clock and the corresponding rate changes of the auxillary clocks of the CPU
22 * registers to acheive a fast co-oridinated rate change for all the CPU domain
23 * clocks.
27 * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
36 #include <linux/clk-provider.h>
37 #include "clk-cpu.h"
101 pr_err("%s: re-parenting mux timed-out\n", __func__); in wait_until_mux_stable()
[all …]
/kernel/linux/linux-4.19/drivers/clk/samsung/
Dclk-cpu.c16 * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
17 * clock for CPU domain. The rates of these auxiliary clocks are related to the
22 * clock and the corresponding rate changes of the auxillary clocks of the CPU
25 * registers to acheive a fast co-oridinated rate change for all the CPU domain
26 * clocks.
30 * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
38 #include <linux/clk-provider.h>
39 #include "clk-cpu.h"
103 pr_err("%s: re-parenting mux timed-out\n", __func__); in wait_until_mux_stable()
106 /* common round rate callback useable for all types of CPU clocks */
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/mmc/
Dmmc-pwrseq-simple.txt8 - compatible : contains "mmc-pwrseq-simple".
11 - reset-gpios : contains a list of GPIO specifiers. The reset GPIOs are asserted
13 They will be de-asserted right after the power has been provided to the
15 - clocks : Must contain an entry for the entry in clock-names.
16 See ../clocks/clock-bindings.txt for details.
17 - clock-names : Must include the following entry:
19 - post-power-on-delay-ms : Delay in ms after powering the card and
20 de-asserting the reset-gpios (if any)
21 - power-off-delay-us : Delay in us after asserting the reset-gpios (if any)
27 compatible = "mmc-pwrseq-simple";
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/hisilicon/
Dhisi-ade.txt1 Device-Tree bindings for hisilicon ADE display controller driver
4 data from memory, do composition, do post image processing, generate RGB
8 - compatible: value should be "hisilicon,hi6220-ade".
9 - reg: physical base address and length of the ADE controller's registers.
10 - hisilicon,noc-syscon: ADE NOC QoS syscon.
11 - resets: The ADE reset controller node.
12 - interrupt: the ldi vblank interrupt number used.
13 - clocks: a list of phandle + clock-specifier pairs, one for each entry
14 in clock-names.
15 - clock-names: should contain:
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/hisilicon/
Dhisi-ade.txt1 Device-Tree bindings for hisilicon ADE display controller driver
4 data from memory, do composition, do post image processing, generate RGB
8 - compatible: value should be "hisilicon,hi6220-ade".
9 - reg: physical base address and length of the ADE controller's registers.
10 - hisilicon,noc-syscon: ADE NOC QoS syscon.
11 - resets: The ADE reset controller node.
12 - interrupt: the ldi vblank interrupt number used.
13 - clocks: a list of phandle + clock-specifier pairs, one for each entry
14 in clock-names.
15 - clock-names: should contain:
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dkeystone-k2e-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
8 clocks {
10 #clock-cells = <0>;
11 compatible = "ti,keystone,main-pll-clock";
12 clocks = <&refclksys>;
14 reg-names = "control", "multiplier", "post-divider";
18 #clock-cells = <0>;
19 compatible = "ti,keystone,pll-clock";
20 clocks = <&refclkpass>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dkeystone-k2e-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
8 clocks {
10 #clock-cells = <0>;
11 compatible = "ti,keystone,main-pll-clock";
12 clocks = <&refclksys>;
14 reg-names = "control", "multiplier", "post-divider";
18 #clock-cells = <0>;
19 compatible = "ti,keystone,pll-clock";
20 clocks = <&refclkpass>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/
Dnvidia,tegra210-ahub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 for audio pre-processing, post-processing and a programmable full
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^ahub@[0-9a-f]*$"
26 - enum:
27 - nvidia,tegra210-ahub
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mailbox/
Dst,stm32-ipcc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 The IPCC block provides a non blocking signaling mechanism to post and
16 - Fabien Dessenne <fabien.dessenne@st.com>
17 - Arnaud Pouliquen <arnaud.pouliquen@st.com>
21 const: st,stm32mp1-ipcc
26 clocks:
31 - description: rx channel occupied
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/mailbox/
Dstm32-ipcc.txt1 * STMicroelectronics STM32 IPCC (Inter-Processor Communication Controller)
3 The IPCC block provides a non blocking signaling mechanism to post and
9 - compatible: Must be "st,stm32mp1-ipcc"
10 - reg: Register address range (base address and length)
11 - st,proc-id: Processor id using the mailbox (0 or 1)
12 - clocks: Input clock
13 - interrupt-names: List of names for the interrupts described by the interrupt
15 - "rx"
16 - "tx"
17 - "wakeup"
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/dsp/
Dfsl,dsp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daniel Baluta <daniel.baluta@nxp.com>
14 advanced pre- and post- audio processing.
19 - fsl,imx8qxp-dsp
20 - fsl,imx8qm-dsp
21 - fsl,imx8mp-dsp
26 clocks:
28 - description: ipg clock
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/
Dhisilicon-femac.txt4 - compatible: should contain one of the following version strings:
5 * "hisilicon,hisi-femac-v1"
6 * "hisilicon,hisi-femac-v2"
7 and the soc string "hisilicon,hi3516cv300-femac".
8 - reg: specifies base physical address(s) and size of the device registers.
11 - interrupts: should contain the MAC interrupt.
12 - clocks: A phandle to the MAC main clock.
13 - resets: should contain the phandle to the MAC reset signal(required) and
15 - reset-names: should contain the reset signal name "mac"(required)
17 - mac-address: see ethernet.txt [1].
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Dmmc-pwrseq-simple.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
19 const: mmc-pwrseq-simple
21 reset-gpios:
28 They will be de-asserted right after the power has been provided to the
31 clocks:
33 description: Handle for the entry in clock-names.
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dhisilicon-femac.txt4 - compatible: should contain one of the following version strings:
5 * "hisilicon,hisi-femac-v1"
6 * "hisilicon,hisi-femac-v2"
7 and the soc string "hisilicon,hi3516cv300-femac".
8 - reg: specifies base physical address(s) and size of the device registers.
11 - interrupts: should contain the MAC interrupt.
12 - clocks: A phandle to the MAC main clock.
13 - resets: should contain the phandle to the MAC reset signal(required) and
15 - reset-names: should contain the reset signal name "mac"(required)
17 - phy-mode: see ethernet.txt [1].
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/
Damlogic,meson-vpu.txt7 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
9 D |-------| |----| | | | | HDMI PLL |
10 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
11 R |-------| |----| Processing | | | | |
12 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
13 R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----|
14 A | osd1 | | | Blenders | | Encl ----------|----|---------------|
15 M |-------|______|----|____________| |________________| | |
20 ---------------------
27 VPP: Video Post Processing
[all …]

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