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/kernel/linux/linux-5.10/drivers/staging/sm750fb/
Dddk750_power.c1 // SPDX-License-Identifier: GPL-2.0
30 * On hardware reset, power mode 0 is default.
58 /* Set up other fields in Power Control Register */ in sm750_set_power_mode()
71 /* Program new power mode. */ in sm750_set_power_mode()
75 void sm750_set_current_gate(unsigned int gate) in sm750_set_current_gate() argument
78 poke32(MODE1_GATE, gate); in sm750_set_current_gate()
80 poke32(MODE0_GATE, gate); in sm750_set_current_gate()
88 u32 gate; in sm750_enable_2d_engine() local
90 gate = peek32(CURRENT_GATE); in sm750_enable_2d_engine()
92 gate |= (CURRENT_GATE_DE | CURRENT_GATE_CSC); in sm750_enable_2d_engine()
[all …]
/kernel/linux/linux-4.19/drivers/staging/sm750fb/
Dddk750_power.c1 // SPDX-License-Identifier: GPL-2.0
30 * On hardware reset, power mode 0 is default.
58 /* Set up other fields in Power Control Register */ in sm750_set_power_mode()
71 /* Program new power mode. */ in sm750_set_power_mode()
75 void sm750_set_current_gate(unsigned int gate) in sm750_set_current_gate() argument
78 poke32(MODE1_GATE, gate); in sm750_set_current_gate()
80 poke32(MODE0_GATE, gate); in sm750_set_current_gate()
88 u32 gate; in sm750_enable_2d_engine() local
90 gate = peek32(CURRENT_GATE); in sm750_enable_2d_engine()
92 gate |= (CURRENT_GATE_DE | CURRENT_GATE_CSC); in sm750_enable_2d_engine()
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/iommu/
Dsamsung,sysmmu.txt4 physical memory chunks visible as a contiguous region to DMA-capable peripheral
5 devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
10 another capabilities like L2 TLB or block-fetch buffers to minimize translation
31 - compatible: Should be "samsung,exynos-sysmmu"
32 - reg: A tuple of base address and size of System MMU registers.
33 - #iommu-cells: Should be <0>.
34 - interrupts: An interrupt specifier for interrupt signal of System MMU,
37 - clock-names: Should be "sysmmu" or a pair of "aclk" and "pclk" to gate
40 another gate clock other core (usually main gate clock
42 - clocks: Phandles for respective clocks described by clock-names.
[all …]
/kernel/linux/linux-5.10/drivers/clk/mxs/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
14 * struct clk_pll - mxs pll clock
17 * @power: the shift of power bit
20 * The mxs pll is a fixed rate clock with power and gate control,
21 * and the shift of gate bit is always 31.
26 u8 power; member
36 writel_relaxed(1 << pll->power, pll->base + SET); in clk_pll_prepare()
47 writel_relaxed(1 << pll->power, pll->base + CLR); in clk_pll_unprepare()
54 writel_relaxed(1 << 31, pll->base + CLR); in clk_pll_enable()
[all …]
/kernel/linux/linux-5.10/drivers/clk/samsung/
Dclk-exynos4412-isp.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/clock/exynos4.h>
12 #include <linux/clk-provider.h>
19 /* Exynos4x12 specific registers, which belong to ISP power domain */
48 GATE(CLK_ISP_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, 0, 0),
49 GATE(CLK_ISP_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, 0, 0),
50 GATE(CLK_ISP_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, 0, 0),
51 GATE(CLK_ISP_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 0, 0),
52 GATE(CLK_ISP_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 0, 0),
53 GATE(CLK_ISP_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 0, 0),
[all …]
/kernel/linux/linux-4.19/drivers/clk/samsung/
Dclk-exynos4412-isp.c12 #include <dt-bindings/clock/exynos4.h>
15 #include <linux/clk-provider.h>
22 /* Exynos4x12 specific registers, which belong to ISP power domain */
51 GATE(CLK_ISP_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, 0, 0),
52 GATE(CLK_ISP_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, 0, 0),
53 GATE(CLK_ISP_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, 0, 0),
54 GATE(CLK_ISP_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 0, 0),
55 GATE(CLK_ISP_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 0, 0),
56 GATE(CLK_ISP_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 0, 0),
57 GATE(CLK_ISP_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, 0, 0),
[all …]
/kernel/linux/linux-4.19/drivers/clk/ingenic/
Djz4770-cgu.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/jz4770-cgu.h>
41 #define LCR_LPM BIT(0) /* Low Power Mode */
47 #define USBPCR1_UHC_POWER BIT(5) /* UHC PHY power down */
53 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_enable()
54 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_enable()
63 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_disable()
64 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_disable()
72 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_is_enabled()
[all …]
/kernel/linux/linux-4.19/drivers/clk/mxs/
Dclk-pll.c8 * http://www.opensource.org/licenses/gpl-license.html
12 #include <linux/clk-provider.h>
20 * struct clk_pll - mxs pll clock
23 * @power: the shift of power bit
26 * The mxs pll is a fixed rate clock with power and gate control,
27 * and the shift of gate bit is always 31.
32 u8 power; member
42 writel_relaxed(1 << pll->power, pll->base + SET); in clk_pll_prepare()
53 writel_relaxed(1 << pll->power, pll->base + CLR); in clk_pll_unprepare()
60 writel_relaxed(1 << 31, pll->base + CLR); in clk_pll_enable()
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-mmp/
Dpm-mmp2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * MMP2 Power Management Routines
18 #include <asm/mach-types.h>
21 #include "addr-map.h"
22 #include "pm-mmp2.h"
23 #include "regs-icu.h"
29 int irq = d->irq; in mmp2_set_wake()
63 /* close AXI fabric clock gate */ in pm_scu_clk_disable()
67 /* close MCB master clock gate */ in pm_scu_clk_disable()
79 /* open AXI fabric clock gate */ in pm_scu_clk_enable()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dimx8qxp-lpcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
10 - Aisheng Dong <aisheng.dong@nxp.com>
13 The Low-Power Clock Gate (LPCG) modules contain a local programming
15 is used to locally gate the clocks for the associated peripheral.
24 include/dt-bindings/clock/imx8-clock.h
29 - fsl,imx8qxp-lpcg-adma
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/iio/gyroscope/
Dinvensense,mpu3050.txt1 Invensense MPU-3050 Gyroscope device tree bindings
4 - compatible : should be "invensense,mpu3050"
5 - reg : the I2C address of the sensor
8 - interrupts : interrupt mapping for the trigger interrupt from the
13 - vdd-supply : supply regulator for the main power voltage.
14 - vlogic-supply : supply regulator for the signal voltage.
15 - mount-matrix : see iio/mount-matrix.txt
18 - The MPU-3050 will pass through and forward the I2C signals from the
21 i2c gate node. For details see: i2c/i2c-gate.txt
28 interrupt-parent = <&foo>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iio/gyroscope/
Dinvensense,mpu3050.txt1 Invensense MPU-3050 Gyroscope device tree bindings
4 - compatible : should be "invensense,mpu3050"
5 - reg : the I2C address of the sensor
8 - interrupts : interrupt mapping for the trigger interrupt from the
13 - vdd-supply : supply regulator for the main power voltage.
14 - vlogic-supply : supply regulator for the signal voltage.
15 - mount-matrix : see iio/mount-matrix.txt
18 - The MPU-3050 will pass through and forward the I2C signals from the
21 i2c gate node. For details see: i2c/i2c-gate.txt
28 interrupt-parent = <&foo>;
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/ti/
Ddpll.txt3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped DPLL with usually two selectable input clocks
10 modes (locked, low power stop etc.) This binding has several
11 sub-types, which effectively result in slightly different setup
14 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be one of:
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ti/
Ddpll.txt3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped DPLL with usually two selectable input clocks
10 modes (locked, low power stop etc.) This binding has several
11 sub-types, which effectively result in slightly different setup
14 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be one of:
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-mmp/
Dpm-mmp2.c2 * MMP2 Power Management Routines
20 #include <asm/mach-types.h>
23 #include "addr-map.h"
24 #include "pm-mmp2.h"
25 #include "regs-icu.h"
31 int irq = d->irq; in mmp2_set_wake()
65 /* close AXI fabric clock gate */ in pm_scu_clk_disable()
69 /* close MCB master clock gate */ in pm_scu_clk_disable()
81 /* open AXI fabric clock gate */ in pm_scu_clk_enable()
85 /* open MCB master clock gate */ in pm_scu_clk_enable()
[all …]
/kernel/linux/linux-5.10/drivers/media/tuners/
Dfc0013.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
11 #include "fc0013-priv.h"
17 .addr = priv->addr, .flags = 0, .buf = buf, .len = 2 in fc0013_writereg()
20 if (i2c_transfer(priv->i2c, &msg, 1) != 1) { in fc0013_writereg()
22 return -EREMOTEIO; in fc0013_writereg()
30 { .addr = priv->addr, .flags = 0, .buf = &reg, .len = 1 }, in fc0013_readreg()
31 { .addr = priv->addr, .flags = I2C_M_RD, .buf = val, .len = 1 }, in fc0013_readreg()
34 if (i2c_transfer(priv->i2c, msg, 2) != 2) { in fc0013_readreg()
36 return -EREMOTEIO; in fc0013_readreg()
[all …]
/kernel/linux/linux-4.19/drivers/media/tuners/
Dfc0013.c4 * Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
21 #include "fc0013-priv.h"
27 .addr = priv->addr, .flags = 0, .buf = buf, .len = 2 in fc0013_writereg()
30 if (i2c_transfer(priv->i2c, &msg, 1) != 1) { in fc0013_writereg()
32 return -EREMOTEIO; in fc0013_writereg()
40 { .addr = priv->addr, .flags = 0, .buf = &reg, .len = 1 }, in fc0013_readreg()
41 { .addr = priv->addr, .flags = I2C_M_RD, .buf = val, .len = 1 }, in fc0013_readreg()
44 if (i2c_transfer(priv->i2c, msg, 2) != 2) { in fc0013_readreg()
46 return -EREMOTEIO; in fc0013_readreg()
53 kfree(fe->tuner_priv); in fc0013_release()
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/hisilicon/hibmc/
Dhibmc_drm_de.c54 #define PADDING(align, data) (((data) + (align) - 1) & (~((align) - 1)))
59 struct drm_framebuffer *fb = state->fb; in hibmc_plane_atomic_check()
60 struct drm_crtc *crtc = state->crtc; in hibmc_plane_atomic_check()
62 u32 src_w = state->src_w >> 16; in hibmc_plane_atomic_check()
63 u32 src_h = state->src_h >> 16; in hibmc_plane_atomic_check()
68 crtc_state = drm_atomic_get_crtc_state(state->state, crtc); in hibmc_plane_atomic_check()
72 if (src_w != state->crtc_w || src_h != state->crtc_h) { in hibmc_plane_atomic_check()
74 return -EINVAL; in hibmc_plane_atomic_check()
77 if (state->crtc_x < 0 || state->crtc_y < 0) { in hibmc_plane_atomic_check()
79 return -EINVAL; in hibmc_plane_atomic_check()
[all …]
/kernel/linux/linux-5.10/include/dt-bindings/clock/
Dhi6220-clock.h1 /* SPDX-License-Identifier: GPL-2.0-only */
41 /* gate clocks */
60 /* gate clock */
124 /* gate clock */
130 /* gate clocks */
161 /* clk in Hi6220 power controller */
162 /* gate clocks */
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dhisilicon-histb-pcie.txt6 Documentation/devicetree/bindings/pci/designware-pcie.txt.
11 - compatible: Should be one of the following strings:
12 "hisilicon,hi3798cv200-pcie"
13 - reg: Should contain sysctl, rc_dbi, config registers location and length.
14 - reg-names: Must include the following entries:
16 "rc-dbi": configuration space of PCIe controller;
18 - bus-range: PCI bus numbers covered.
19 - interrupts: MSI interrupt.
20 - interrupt-names: Must include "msi" entries.
21 - clocks: List of phandle and clock specifier pairs as listed in clock-names
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/pci/
Dhisilicon-histb-pcie.txt6 Documentation/devicetree/bindings/pci/designware-pcie.txt.
11 - compatible: Should be one of the following strings:
12 "hisilicon,hi3798cv200-pcie"
13 - reg: Should contain sysctl, rc_dbi, config registers location and length.
14 - reg-names: Must include the following entries:
16 "rc-dbi": configuration space of PCIe controller;
18 - bus-range: PCI bus numbers covered.
19 - interrupts: MSI interrupt.
20 - interrupt-names: Must include "msi" entries.
21 - clocks: List of phandle and clock specifier pairs as listed in clock-names
[all …]
/kernel/linux/linux-5.10/drivers/clk/pxa/
Dclk-pxa.h1 /* SPDX-License-Identifier: GPL-2.0-only */
92 * - a low power parent
93 * - a normal parent
95 * +------------+ +-----------+
96 * | Low Power | --- | x mult_lp |
98 * +------------+ +-----------+ \+-----+ +-----------+
99 * | Mux |---| CKEN gate |
100 * +------------+ +-----------+ /+-----+ +-----------+
101 * | High Power | | x mult_hp |/
102 * | Clock | --- | / div_hp |
[all …]
/kernel/linux/linux-4.19/drivers/clk/pxa/
Dclk-pxa.h96 * - a low power parent
97 * - a normal parent
99 * +------------+ +-----------+
100 * | Low Power | --- | x mult_lp |
102 * +------------+ +-----------+ \+-----+ +-----------+
103 * | Mux |---| CKEN gate |
104 * +------------+ +-----------+ /+-----+ +-----------+
105 * | High Power | | x mult_hp |/
106 * | Clock | --- | / div_hp |
107 * +------------+ +-----------+
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-tegra/
Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-tegra/platsmp.c
26 #include <asm/mach-types.h>
50 * power-gated via the flow controller). This will have no in tegra20_boot_secondary()
58 * power-gate the CPU this will cause the flow controller to in tegra20_boot_secondary()
80 * The power up sequence of cold boot CPU and warm boot CPU in tegra30_boot_secondary()
84 * power will be resumed automatically after un-halting the in tegra30_boot_secondary()
103 * The power status of the cold boot CPU is power gated as in tegra30_boot_secondary()
104 * default. To power up the cold boot CPU, the power should in tegra30_boot_secondary()
105 * be un-gated by un-toggling the power gate register in tegra30_boot_secondary()
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-tegra/
Dplatsmp.c2 * linux/arch/arm/mach-tegra/platsmp.c
29 #include <asm/mach-types.h>
53 * power-gated via the flow controller). This will have no in tegra20_boot_secondary()
61 * power-gate the CPU this will cause the flow controller to in tegra20_boot_secondary()
83 * The power up sequence of cold boot CPU and warm boot CPU in tegra30_boot_secondary()
87 * power will be resumed automatically after un-halting the in tegra30_boot_secondary()
106 * The power status of the cold boot CPU is power gated as in tegra30_boot_secondary()
107 * default. To power up the cold boot CPU, the power should in tegra30_boot_secondary()
108 * be un-gated by un-toggling the power gate register in tegra30_boot_secondary()
141 * The flow controller in charge of the power state and in tegra114_boot_secondary()
[all …]

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