| /kernel/linux/linux-5.10/drivers/cpuidle/ |
| D | cpuidle-cps.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <asm/pm-cps.h>
17 STATE_NC_WAIT, /* MIPS wait instruction, non-coherent */
18 STATE_CLOCK_GATED, /* Core clock gated */
19 STATE_POWER_GATED, /* Core power gated */
36 if (cpus_are_siblings(0, dev->cpu) && (index > STATE_NC_WAIT)) in cps_nc_enter()
52 return -EINVAL; in cps_nc_enter()
55 /* Notify listeners the CPU is about to power down */ in cps_nc_enter()
57 return -EINTR; in cps_nc_enter()
78 .name = "nc-wait",
[all …]
|
| /kernel/linux/linux-4.19/drivers/cpuidle/ |
| D | cpuidle-cps.c | 16 #include <asm/pm-cps.h>
21 STATE_NC_WAIT, /* MIPS wait instruction, non-coherent */
22 STATE_CLOCK_GATED, /* Core clock gated */
23 STATE_POWER_GATED, /* Core power gated */
40 if (cpus_are_siblings(0, dev->cpu) && (index > STATE_NC_WAIT)) in cps_nc_enter()
56 return -EINVAL; in cps_nc_enter()
59 /* Notify listeners the CPU is about to power down */ in cps_nc_enter()
61 return -EINTR; in cps_nc_enter()
82 .name = "nc-wait",
83 .desc = "non-coherent MIPS wait",
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mach-tegra/ |
| D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-tegra/platsmp.c
26 #include <asm/mach-types.h>
50 * power-gated via the flow controller). This will have no in tegra20_boot_secondary()
58 * power-gate the CPU this will cause the flow controller to in tegra20_boot_secondary()
80 * The power up sequence of cold boot CPU and warm boot CPU in tegra30_boot_secondary()
84 * power will be resumed automatically after un-halting the in tegra30_boot_secondary()
103 * The power status of the cold boot CPU is power gated as in tegra30_boot_secondary()
104 * default. To power up the cold boot CPU, the power should in tegra30_boot_secondary()
105 * be un-gated by un-toggling the power gate register in tegra30_boot_secondary()
[all …]
|
| /kernel/linux/linux-4.19/arch/arm/mach-tegra/ |
| D | platsmp.c | 2 * linux/arch/arm/mach-tegra/platsmp.c
29 #include <asm/mach-types.h>
53 * power-gated via the flow controller). This will have no in tegra20_boot_secondary()
61 * power-gate the CPU this will cause the flow controller to in tegra20_boot_secondary()
83 * The power up sequence of cold boot CPU and warm boot CPU in tegra30_boot_secondary()
87 * power will be resumed automatically after un-halting the in tegra30_boot_secondary()
106 * The power status of the cold boot CPU is power gated as in tegra30_boot_secondary()
107 * default. To power up the cold boot CPU, the power should in tegra30_boot_secondary()
108 * be un-gated by un-toggling the power gate register in tegra30_boot_secondary()
141 * The flow controller in charge of the power state and in tegra114_boot_secondary()
[all …]
|
| /kernel/linux/linux-5.10/arch/mips/include/asm/ |
| D | pm-cps.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 * The CM & CPC can only handle coherence & power control on a per-core basis,
25 CPS_PM_NC_WAIT, /* MIPS wait instruction, non-coherent */
26 CPS_PM_CLOCK_GATED, /* Core clock gated */
27 CPS_PM_POWER_GATED, /* Core power gated */
32 * cps_pm_support_state - determine whether the system supports a PM state
40 * cps_pm_enter_state - enter a PM state
43 * Enter the given PM state. If coupled_coherence is non-zero then it is
45 * each coupled CPU. Returns 0 on successful entry & exit, otherwise -errno.
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,idle-state.txt | 3 ARM provides idle-state node to define the cpuidle states, as defined in [1].
4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
6 The idle states supported by the QCOM SoC are defined as -
10 * Standalone Power Collapse (Standalone PC or SPC)
11 * Power Collapse (PC)
26 Retention: Retention is a low power state where the core is clock gated and
33 Standalone PC: A cpu can power down and warmboot if there is a sufficient time
35 to indicate a core entering a power down state without consulting any other
36 cpu or the system resources. This helps save power only on that core. The SPM
37 sequence for this idle state is programmed to power down the supply to the
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,idle-state.txt | 3 ARM provides idle-state node to define the cpuidle states, as defined in [1].
4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
6 The idle states supported by the QCOM SoC are defined as -
10 * Standalone Power Collapse (Standalone PC or SPC)
11 * Power Collapse (PC)
26 Retention: Retention is a low power state where the core is clock gated and
33 Standalone PC: A cpu can power down and warmboot if there is a sufficient time
35 to indicate a core entering a power down state without consulting any other
36 cpu or the system resources. This helps save power only on that core. The SPM
37 sequence for this idle state is programmed to power down the supply to the
[all …]
|
| /kernel/linux/linux-4.19/arch/mips/include/asm/ |
| D | pm-cps.h | 15 * The CM & CPC can only handle coherence & power control on a per-core basis,
29 CPS_PM_NC_WAIT, /* MIPS wait instruction, non-coherent */
30 CPS_PM_CLOCK_GATED, /* Core clock gated */
31 CPS_PM_POWER_GATED, /* Core power gated */
36 * cps_pm_support_state - determine whether the system supports a PM state
44 * cps_pm_enter_state - enter a PM state
47 * Enter the given PM state. If coupled_coherence is non-zero then it is
49 * each coupled CPU. Returns 0 on successful entry & exit, otherwise -errno.
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/ |
| D | st,stm32-rcc.txt | 6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 - reg: should be register base and length as documented in the
16 - #reset-cells: 1, see below
17 - #clock-cells: 2, device nodes should specify the clock in their "clocks"
19 between gated clocks and other clocks and an index specifying the clock to
21 - clocks: External oscillator clock phandle
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | st,stm32-rcc.txt | 6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
16 - reg: should be register base and length as documented in the
18 - #reset-cells: 1, see below
19 - #clock-cells: 2, device nodes should specify the clock in their "clocks"
21 between gated clocks and other clocks and an index specifying the clock to
[all …]
|
| /kernel/linux/linux-5.10/drivers/staging/media/atomisp/pci/ |
| D | atomisp-regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
56 * Enables the combining of adjacent 32-byte read requests to the same
57 * cache line. When cleared, each 32-byte read request is sent as a
64 * If cleared, the high speed clock going to the digital logic is gated when
65 * RCOMP update is happening. The clock is gated for a minimum of 100 nsec.
66 * If this bit is set, then the high speed clock is not gated during the
72 * Enables the combining of adjacent 32-byte write requests to the same
73 * cache line. When cleared, each 32-byte write request is sent as a
102 /* MRFLD ISP POWER related */
|
| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| D | toshsd.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 #define SD_PCICFG_GATEDCLK 0x41 /* Gated clock */
22 #define SD_PCICFG_EXTGATECLK1 0xf0 /* Could be used for gated clock */
23 #define SD_PCICFG_EXTGATECLK2 0xf1 /* Could be used for gated clock */
34 #define SD_PCICFG_PWR1_OFF 0x00 /* Turn off power */
|
| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | clkt2xxx_dpll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP2-specific DPLL control functions
16 #include "cm-regbits-24xx.h"
21 * _allow_idle - enable DPLL autoidle bits
24 * Enable DPLL automatic idle control. The DPLL will enter low-power
25 * stop when its downstream clocks are gated. No return value.
26 * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
31 if (!clk || !clk->dpll_data) in _allow_idle()
38 * _deny_idle - prevent DPLL from automatically idling
45 if (!clk || !clk->dpll_data) in _deny_idle()
|
| /kernel/linux/linux-4.19/arch/arm/mach-omap2/ |
| D | clkt2xxx_dpll.c | 2 * OMAP2-specific DPLL control functions
19 #include "cm-regbits-24xx.h"
24 * _allow_idle - enable DPLL autoidle bits
27 * Enable DPLL automatic idle control. The DPLL will enter low-power
28 * stop when its downstream clocks are gated. No return value.
29 * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
34 if (!clk || !clk->dpll_data) in _allow_idle()
41 * _deny_idle - prevent DPLL from automatically idling
48 if (!clk || !clk->dpll_data) in _deny_idle()
|
| /kernel/linux/linux-4.19/drivers/staging/rtl8723bs/include/ |
| D | hal_pwr_seq.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
8 Check document WM-20130815-JackieLau-RTL8723B_Power_Architecture v08.vsd
9 There are 6 HW Power States:
10 0: POFF--Power Off
11 1: PDN--Power Down
12 2: CARDEMU--Card Emulation
13 3: ACT--Active Mode
14 4: LPS--Low Power State
15 5: SUS--Suspend
50 …LL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
[all …]
|
| /kernel/linux/linux-5.10/drivers/staging/rtl8723bs/include/ |
| D | hal_pwr_seq.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
8 Check document WM-20130815-JackieLau-RTL8723B_Power_Architecture v08.vsd
9 There are 6 HW Power States:
10 0: POFF--Power Off
11 1: PDN--Power Down
12 2: CARDEMU--Card Emulation
13 3: ACT--Active Mode
14 4: LPS--Low Power State
15 5: SUS--Suspend
50 …LL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/iommu/ |
| D | samsung,sysmmu.txt | 4 physical memory chunks visible as a contiguous region to DMA-capable peripheral
5 devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
10 another capabilities like L2 TLB or block-fetch buffers to minimize translation
31 - compatible: Should be "samsung,exynos-sysmmu"
32 - reg: A tuple of base address and size of System MMU registers.
33 - #iommu-cells: Should be <0>.
34 - interrupts: An interrupt specifier for interrupt signal of System MMU,
37 - clock-names: Should be "sysmmu" or a pair of "aclk" and "pclk" to gate
39 Optional "master" if the clock to the System MMU is gated by
42 - clocks: Phandles for respective clocks described by clock-names.
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mach-s3c/ |
| D | cpuidle-s3c64xx.c | 1 // SPDX-License-Identifier: GPL-2.0
19 #include "regs-sys-s3c64xx.h"
20 #include "regs-syscon-power-s3c64xx.h"
48 .desc = "System active, ARM gated",
|
| /kernel/linux/linux-4.19/arch/arm/mach-s3c64xx/ |
| D | cpuidle.c | 1 // SPDX-License-Identifier: GPL-2.0
19 #include "regs-sys.h"
20 #include "regs-syscon-power.h"
48 .desc = "System active, ARM gated",
|
| /kernel/linux/linux-4.19/Documentation/arm/sunxi/ |
| D | clocks.txt | 10 A: The 24MHz oscillator allows gating to save power. Indeed, if gated
48 A: The linux-sunxi wiki contains a page documenting the clock registers,
51 http://linux-sunxi.org/A10/CCM
56 https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.0/arch/arm/mach-sun4i/clock/ccmu
|
| /kernel/linux/linux-4.19/drivers/platform/x86/ |
| D | intel_pmc_core.c | 2 * Intel Core SoC Power Management Controller Driver
32 #include <asm/intel-family.h>
71 {"OPI-DMI", SPT_PMC_BIT_OPI},
79 {"HDA-PGD0", SPT_PMC_BIT_HDA_PGD0},
80 {"HDA-PGD1", SPT_PMC_BIT_HDA_PGD1},
81 {"HDA-PGD2", SPT_PMC_BIT_HDA_PGD2},
82 {"HDA-PGD3", SPT_PMC_BIT_HDA_PGD3},
95 {"USB3-OTG", SPT_PMC_BIT_USB3_OTG},
129 {"OPI-DMI", BIT(1)},
270 return readb(pmcdev->regbase + offset); in pmc_core_reg_read_byte()
[all …]
|
| /kernel/linux/linux-5.10/include/linux/pinctrl/ |
| D | pinctrl-state.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
25 * but not fully sleeping - some power may be on but clocks gated for
|
| /kernel/linux/linux-4.19/include/linux/pinctrl/ |
| D | pinctrl-state.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
22 * but not fully sleeping - some power may be on but clocks gated for
|
| /kernel/linux/linux-5.10/arch/arm/include/asm/ |
| D | mcpm.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright: (C) 2012-2013 Linaro Limited
40 * branch once it is ready to re-enter the kernel using ptr, or NULL if it
41 * should be gated. A gated CPU is held in a WFE loop until its vector
55 * CPU/cluster power operations API for higher subsystems to use.
59 * mcpm_is_available - returns whether MCPM is initialized and available
66 * mcpm_cpu_power_up - make given CPU in given cluster runable
87 * mcpm_cpu_power_down - power the calling CPU down
92 * then the cluster is prepared for power-down too.
96 * On success this does not return. Re-entry in the kernel is expected
[all …]
|
| /kernel/linux/linux-4.19/arch/arm/include/asm/ |
| D | mcpm.h | 5 * Copyright: (C) 2012-2013 Linaro Limited
43 * branch once it is ready to re-enter the kernel using ptr, or NULL if it
44 * should be gated. A gated CPU is held in a WFE loop until its vector
58 * CPU/cluster power operations API for higher subsystems to use.
62 * mcpm_is_available - returns whether MCPM is initialized and available
69 * mcpm_cpu_power_up - make given CPU in given cluster runable
90 * mcpm_cpu_power_down - power the calling CPU down
95 * then the cluster is prepared for power-down too.
99 * On success this does not return. Re-entry in the kernel is expected
106 * mcpm_wait_for_cpu_powerdown() subsequently returns non-zero for the
[all …]
|