| /kernel/linux/linux-4.19/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_atombios.c | 568 struct amdgpu_pll *ppll = &adev->clock.ppll[0]; in amdgpu_atombios_get_clock_info() local
575 ppll->reference_freq = in amdgpu_atombios_get_clock_info()
577 ppll->reference_div = 0; in amdgpu_atombios_get_clock_info()
579 ppll->pll_out_min = in amdgpu_atombios_get_clock_info()
581 ppll->pll_out_max = in amdgpu_atombios_get_clock_info()
584 ppll->lcd_pll_out_min = in amdgpu_atombios_get_clock_info()
586 if (ppll->lcd_pll_out_min == 0) in amdgpu_atombios_get_clock_info()
587 ppll->lcd_pll_out_min = ppll->pll_out_min; in amdgpu_atombios_get_clock_info()
588 ppll->lcd_pll_out_max = in amdgpu_atombios_get_clock_info()
590 if (ppll->lcd_pll_out_max == 0) in amdgpu_atombios_get_clock_info()
[all …]
|
| D | amdgpu_pll.c | 279 * amdgpu_pll_get_shared_dp_ppll - return the PPLL used by another crtc for DP
283 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
284 * also in DP mode. For DP, a single PPLL can be used for all DP
308 * amdgpu_pll_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
313 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
|
| D | dce_v8_0.c | 2082 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2086 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2087 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2088 * monitors a dedicated PPLL must be used. If a particular board has
2113 /* skip PPLL programming if using ext clock */ in dce_v8_0_pick_pll()
2116 /* use the same PPLL for all DP monitors */ in dce_v8_0_pick_pll()
2122 /* use the same PPLL for all monitors with the same clock */ in dce_v8_0_pick_pll()
2136 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v8_0_pick_pll()
2147 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v8_0_pick_pll()
2459 /* disable the ppll */ in dce_v8_0_crtc_disable()
[all …]
|
| D | dce_v11_0.c | 2224 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2228 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2229 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2230 * monitors a dedicated PPLL must be used. If a particular board has
2291 /* skip PPLL programming if using ext clock */ in dce_v11_0_pick_pll()
2294 /* use the same PPLL for all DP monitors */ in dce_v11_0_pick_pll()
2300 /* use the same PPLL for all monitors with the same clock */ in dce_v11_0_pick_pll()
2313 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v11_0_pick_pll()
2322 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v11_0_pick_pll()
2637 /* disable the ppll */ in dce_v11_0_crtc_disable()
[all …]
|
| D | dce_v10_0.c | 2191 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2195 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2196 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2197 * monitors a dedicated PPLL must be used. If a particular board has
2222 /* skip PPLL programming if using ext clock */ in dce_v10_0_pick_pll()
2225 /* use the same PPLL for all DP monitors */ in dce_v10_0_pick_pll()
2231 /* use the same PPLL for all monitors with the same clock */ in dce_v10_0_pick_pll()
2245 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v10_0_pick_pll()
2558 /* disable the ppll */ in dce_v10_0_crtc_disable()
2621 /* if we can't get a PPLL for a non-DP encoder, fail */ in dce_v10_0_crtc_mode_fixup()
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_atombios.c | 569 struct amdgpu_pll *ppll = &adev->clock.ppll[0]; in amdgpu_atombios_get_clock_info() local
576 ppll->reference_freq = in amdgpu_atombios_get_clock_info()
578 ppll->reference_div = 0; in amdgpu_atombios_get_clock_info()
580 ppll->pll_out_min = in amdgpu_atombios_get_clock_info()
582 ppll->pll_out_max = in amdgpu_atombios_get_clock_info()
585 ppll->lcd_pll_out_min = in amdgpu_atombios_get_clock_info()
587 if (ppll->lcd_pll_out_min == 0) in amdgpu_atombios_get_clock_info()
588 ppll->lcd_pll_out_min = ppll->pll_out_min; in amdgpu_atombios_get_clock_info()
589 ppll->lcd_pll_out_max = in amdgpu_atombios_get_clock_info()
591 if (ppll->lcd_pll_out_max == 0) in amdgpu_atombios_get_clock_info()
[all …]
|
| D | amdgpu_pll.c | 279 * amdgpu_pll_get_shared_dp_ppll - return the PPLL used by another crtc for DP
283 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
284 * also in DP mode. For DP, a single PPLL can be used for all DP
308 * amdgpu_pll_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
313 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
|
| D | dce_v8_0.c | 2118 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2122 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2123 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2124 * monitors a dedicated PPLL must be used. If a particular board has
2149 /* skip PPLL programming if using ext clock */ in dce_v8_0_pick_pll()
2152 /* use the same PPLL for all DP monitors */ in dce_v8_0_pick_pll()
2158 /* use the same PPLL for all monitors with the same clock */ in dce_v8_0_pick_pll()
2172 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v8_0_pick_pll()
2183 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v8_0_pick_pll()
2499 /* disable the ppll */ in dce_v8_0_crtc_disable()
[all …]
|
| D | dce_v11_0.c | 2261 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2265 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2266 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2267 * monitors a dedicated PPLL must be used. If a particular board has
2328 /* skip PPLL programming if using ext clock */ in dce_v11_0_pick_pll()
2331 /* use the same PPLL for all DP monitors */ in dce_v11_0_pick_pll()
2337 /* use the same PPLL for all monitors with the same clock */ in dce_v11_0_pick_pll()
2350 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v11_0_pick_pll()
2359 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v11_0_pick_pll()
2678 /* disable the ppll */ in dce_v11_0_crtc_disable()
[all …]
|
| D | atombios_crtc.c | 837 pll = &adev->clock.ppll[0]; in amdgpu_atombios_crtc_set_pll()
840 pll = &adev->clock.ppll[1]; in amdgpu_atombios_crtc_set_pll()
845 pll = &adev->clock.ppll[2]; in amdgpu_atombios_crtc_set_pll()
|
| /kernel/linux/linux-4.19/drivers/gpu/drm/radeon/ |
| D | atombios_crtc.c | 1726 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1730 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1731 * also in DP mode. For DP, a single PPLL can be used for all DP
1760 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1765 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1811 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1815 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1816 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1817 * monitors a dedicated PPLL must be used. If a particular board has
1860 /* skip PPLL programming if using ext clock */ in radeon_atom_pick_pll()
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| D | atombios_crtc.c | 1753 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1757 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1758 * also in DP mode. For DP, a single PPLL can be used for all DP
1787 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1792 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1838 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1842 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1843 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1844 * monitors a dedicated PPLL must be used. If a particular board has
1887 /* skip PPLL programming if using ext clock */ in radeon_atom_pick_pll()
[all …]
|
| /kernel/linux/linux-4.19/drivers/staging/sm750fb/ |
| D | ddk750_chip.c | 386 unsigned int sm750_format_pll_reg(struct pll_value *pPLL) in sm750_format_pll_reg() argument
389 unsigned int POD = pPLL->POD; in sm750_format_pll_reg()
391 unsigned int OD = pPLL->OD; in sm750_format_pll_reg()
392 unsigned int M = pPLL->M; in sm750_format_pll_reg()
393 unsigned int N = pPLL->N; in sm750_format_pll_reg()
|
| D | ddk750_chip.h | 98 unsigned int sm750_format_pll_reg(struct pll_value *pPLL);
|
| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | clk-imx35.c | 61 static const char *std_sel[] = {"ppll", "arm"};
65 /* 0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, enumerator
110 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); in _mx35_clocks_init()
|
| /kernel/linux/linux-5.10/drivers/clk/rockchip/ |
| D | clk-rk3399.c | 23 ppll, enumerator
136 PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" };
140 "ppll" };
145 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll",
150 "ppll", "upll", "xin24m" };
210 PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" };
211 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
236 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
1405 GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0,
1426 COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0,
[all …]
|
| /kernel/linux/linux-4.19/drivers/clk/rockchip/ |
| D | clk-rk3399.c | 29 ppll, enumerator
142 PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" };
146 "ppll" };
151 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll",
156 "ppll", "upll", "xin24m" };
216 PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" };
217 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
242 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
1408 GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0,
1429 COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0,
[all …]
|
| /kernel/linux/linux-4.19/drivers/clk/imx/ |
| D | clk-imx35.c | 65 static const char *std_sel[] = {"ppll", "arm"};
69 /* 0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, enumerator
122 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); in _mx35_clocks_init()
|
| /kernel/linux/linux-4.19/drivers/gpu/drm/amd/display/include/ |
| D | bios_parser_types.h | 198 * other ppll params */
201 * other ppll params */
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/include/ |
| D | bios_parser_types.h | 206 * other ppll params */
209 * other ppll params */
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/ |
| D | imx35-clock.txt | 17 ppll 2
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | imx35-clock.yaml | 21 ppll 2
|
| /kernel/linux/linux-5.10/include/dt-bindings/clock/ |
| D | xlnx-versal-clk.h | 19 #define PPLL 10 macro
|
| /kernel/linux/linux-4.19/drivers/video/fbdev/aty/ |
| D | radeon_base.c | 1374 /* We still have to force a switch to selected PPLL div thanks to in radeon_write_pll_regs()
1386 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ in radeon_write_pll_regs()
1389 /* Reset PPLL & enable atomic update */ in radeon_write_pll_regs()
1394 /* Switch to selected PPLL divider */ in radeon_write_pll_regs()
1401 /* Set PPLL ref. div */ in radeon_write_pll_regs()
1420 /* Set PPLL divider 3 & post divider*/ in radeon_write_pll_regs()
1446 /* Switch back VCLK source to PPLL */ in radeon_write_pll_regs()
1841 /* Calculate PPLL value if necessary */ in radeonfb_set_par()
|
| /kernel/linux/linux-5.10/drivers/video/fbdev/aty/ |
| D | radeon_base.c | 1364 /* We still have to force a switch to selected PPLL div thanks to in radeon_write_pll_regs()
1376 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ in radeon_write_pll_regs()
1379 /* Reset PPLL & enable atomic update */ in radeon_write_pll_regs()
1384 /* Switch to selected PPLL divider */ in radeon_write_pll_regs()
1391 /* Set PPLL ref. div */ in radeon_write_pll_regs()
1410 /* Set PPLL divider 3 & post divider*/ in radeon_write_pll_regs()
1436 /* Switch back VCLK source to PPLL */ in radeon_write_pll_regs()
1825 /* Calculate PPLL value if necessary */ in radeonfb_set_par()
|