Searched +full:pwm +full:- +full:names (Results 1 – 25 of 1071) sorted by relevance
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pwm/ |
| D | pwm.txt | 1 Specifying PWM information for devices
4 1) PWM user nodes
5 -----------------
7 PWM users should specify a list of PWM devices that they want to use
8 with a property containing a 'pwm-list':
10 pwm-list ::= <single-pwm> [pwm-list]
11 single-pwm ::= <pwm-phandle> <pwm-specifier>
12 pwm-phandle : phandle to PWM controller node
13 pwm-specifier : array of #pwm-cells specifying the given PWM
16 PWM properties should be named "pwms". The exact meaning of each pwms
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| D | nvidia,tegra20-pwm.txt | 4 - compatible: Must be:
5 - "nvidia,tegra20-pwm": for Tegra20
6 - "nvidia,tegra30-pwm", "nvidia,tegra20-pwm": for Tegra30
7 - "nvidia,tegra114-pwm", "nvidia,tegra20-pwm": for Tegra114
8 - "nvidia,tegra124-pwm", "nvidia,tegra20-pwm": for Tegra124
9 - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132
10 - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210
11 - "nvidia,tegra186-pwm": for Tegra186
12 - "nvidia,tegra194-pwm": for Tegra194
13 - reg: physical base address and length of the controller's registers
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| D | pwm-mediatek.txt | 1 MediaTek PWM controller
4 - compatible: should be "mediatek,<name>-pwm":
5 - "mediatek,mt2712-pwm": found on mt2712 SoC.
6 - "mediatek,mt7622-pwm": found on mt7622 SoC.
7 - "mediatek,mt7623-pwm": found on mt7623 SoC.
8 - "mediatek,mt7628-pwm": found on mt7628 SoC.
9 - "mediatek,mt7629-pwm": found on mt7629 SoC.
10 - "mediatek,mt8516-pwm": found on mt8516 SoC.
11 - reg: physical base address and length of the controller's registers.
12 - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
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| D | pwm-samsung.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-samsung.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC PWM timers
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 Samsung SoCs contain PWM timer blocks which can be used for system clock source
15 and clock event timers, as well as to drive SoC outputs with PWM signal. Each
16 PWM timer block provides 5 PWM channels (not all of them can drive physical
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| D | pwm-fsl-ftm.txt | 1 Freescale FlexTimer Module (FTM) PWM controller
3 The same FTM PWM device can have a different endianness on different SoCs. The
6 for the endianness of the FTM PWM block as integrated into the existing SoCs:
8 SoC | FTM-PWM endianness
9 --------+-------------------
19 - compatible : should be "fsl,<soc>-ftm-pwm" and one of the following
21 - "fsl,vf610-ftm-pwm" for PWM compatible with the one integrated on VF610
22 - "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM
23 - reg: Physical base address and length of the controller's registers
24 - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
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| D | pwm-mtk-disp.txt | 1 MediaTek display PWM controller
4 - compatible: should be "mediatek,<name>-disp-pwm":
5 - "mediatek,mt2701-disp-pwm": found on mt2701 SoC.
6 - "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
7 - "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
8 - reg: physical base address and length of the controller's registers.
9 - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
11 - clocks: phandle and clock specifier of the PWM reference clock.
12 - clock-names: must contain the following:
13 - "main": clock used to generate PWM signals.
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| D | allwinner,sun4i-a10-pwm.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/allwinner,sun4i-a10-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 PWM Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#pwm-cells":
19 - const: allwinner,sun4i-a10-pwm
20 - const: allwinner,sun5i-a10s-pwm
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| D | pwm-st.txt | 1 STMicroelectronics PWM driver bindings
2 --------------------------------------
5 - compatible : "st,pwm"
6 - #pwm-cells : Number of cells used to specify a PWM. First cell
7 specifies the per-chip index of the PWM to use and the
8 second cell is the period in nanoseconds - fixed to 2
10 - reg : Physical base address and length of the controller's
12 - pinctrl-names: Set to "default".
13 - pinctrl-0: List of phandles pointing to pin configuration nodes
14 for PWM module.
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/pwm/ |
| D | pwm.txt | 1 Specifying PWM information for devices
4 1) PWM user nodes
5 -----------------
7 PWM users should specify a list of PWM devices that they want to use
8 with a property containing a 'pwm-list':
10 pwm-list ::= <single-pwm> [pwm-list]
11 single-pwm ::= <pwm-phandle> <pwm-specifier>
12 pwm-phandle : phandle to PWM controller node
13 pwm-specifier : array of #pwm-cells specifying the given PWM
16 PWM properties should be named "pwms". The exact meaning of each pwms
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| D | pwm-samsung.txt | 1 * Samsung PWM timers
3 Samsung SoCs contain PWM timer blocks which can be used for system clock source
4 and clock event timers, as well as to drive SoC outputs with PWM signal. Each
5 PWM timer block provides 5 PWM channels (not all of them can drive physical
6 outputs - see SoC and board manual).
11 - compatible : should be one of following:
12 samsung,s3c2410-pwm - for 16-bit timers present on S3C24xx SoCs
13 samsung,s3c6400-pwm - for 32-bit timers present on S3C64xx SoCs
14 samsung,s5p6440-pwm - for 32-bit timers present on S5P64x0 SoCs
15 samsung,s5pc100-pwm - for 32-bit timers present on S5PC100, S5PV210,
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| D | nvidia,tegra20-pwm.txt | 4 - compatible: Must be:
5 - "nvidia,tegra20-pwm": for Tegra20
6 - "nvidia,tegra30-pwm", "nvidia,tegra20-pwm": for Tegra30
7 - "nvidia,tegra114-pwm", "nvidia,tegra20-pwm": for Tegra114
8 - "nvidia,tegra124-pwm", "nvidia,tegra20-pwm": for Tegra124
9 - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132
10 - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210
11 - "nvidia,tegra186-pwm": for Tegra186
12 - reg: physical base address and length of the controller's registers
13 - #pwm-cells: should be 2. See pwm.txt in this directory for a description of
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| D | pwm-mediatek.txt | 1 MediaTek PWM controller
4 - compatible: should be "mediatek,<name>-pwm":
5 - "mediatek,mt2712-pwm": found on mt2712 SoC.
6 - "mediatek,mt7622-pwm": found on mt7622 SoC.
7 - "mediatek,mt7623-pwm": found on mt7623 SoC.
8 - "mediatek,mt7628-pwm": found on mt7628 SoC.
9 - reg: physical base address and length of the controller's registers.
10 - #pwm-cells: must be 2. See pwm.txt in this directory for a description of
12 - clocks: phandle and clock specifier of the PWM reference clock.
13 - clock-names: must contain the following, except for MT7628 which
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| D | pwm-fsl-ftm.txt | 1 Freescale FlexTimer Module (FTM) PWM controller
3 The same FTM PWM device can have a different endianness on different SoCs. The
6 for the endianness of the FTM PWM block as integrated into the existing SoCs:
8 SoC | FTM-PWM endianness
9 --------+-------------------
19 - compatible : should be "fsl,<soc>-ftm-pwm" and one of the following
21 - "fsl,vf610-ftm-pwm" for PWM compatible with the one integrated on VF610
22 - "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM
23 - reg: Physical base address and length of the controller's registers
24 - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
[all …]
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| D | pwm-mtk-disp.txt | 1 MediaTek display PWM controller
4 - compatible: should be "mediatek,<name>-disp-pwm":
5 - "mediatek,mt2701-disp-pwm": found on mt2701 SoC.
6 - "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
7 - "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
8 - reg: physical base address and length of the controller's registers.
9 - #pwm-cells: must be 2. See pwm.txt in this directory for a description of
11 - clocks: phandle and clock specifier of the PWM reference clock.
12 - clock-names: must contain the following:
13 - "main": clock used to generate PWM signals.
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| D | pwm-st.txt | 1 STMicroelectronics PWM driver bindings
2 --------------------------------------
5 - compatible : "st,pwm"
6 - #pwm-cells : Number of cells used to specify a PWM. First cell
7 specifies the per-chip index of the PWM to use and the
8 second cell is the period in nanoseconds - fixed to 2
10 - reg : Physical base address and length of the controller's
12 - pinctrl-names: Set to "default".
13 - pinctrl-0: List of phandles pointing to pin configuration nodes
14 for PWM module.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | nvidia,tegra124-dfll.txt | 4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 the fast CPU cluster. It consists of a free-running voltage controlled
10 communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
13 - compatible : should be one of:
14 - "nvidia,tegra124-dfll": for Tegra124
15 - "nvidia,tegra210-dfll": for Tegra210
16 - reg : Defines the following set of registers, in the order listed:
17 - registers for the DFLL control logic.
18 - registers for the I2C output logic.
19 - registers for the integrated I2C master controller.
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | rv1108.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/rv1108-cru.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 interrupt-parent = <&gic>;
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| D | stm32mp157c.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/input/ |
| D | pwm-vibrator.txt | 1 * PWM vibrator device tree bindings
3 Registers a PWM device as vibrator. It is expected, that the vibrator's
4 strength increases based on the duty cycle of the enable PWM channel
7 The binding supports an optional direction PWM channel, that can be
12 - compatible: should contain "pwm-vibrator"
13 - pwm-names: Should contain "enable" and optionally "direction"
14 - pwms: Should contain a PWM handle for each entry in pwm-names
17 - vcc-supply: Phandle for the regulator supplying power
18 - direction-duty-cycle-ns: Duty cycle of the direction PWM channel in
26 pinctrl-single,pins = <
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/input/ |
| D | pwm-vibrator.txt | 1 * PWM vibrator device tree bindings
3 Registers a PWM device as vibrator. It is expected, that the vibrator's
4 strength increases based on the duty cycle of the enable PWM channel
7 The binding supports an optional direction PWM channel, that can be
12 - compatible: should contain "pwm-vibrator"
13 - pwm-names: Should contain "enable" and optionally "direction"
14 - pwms: Should contain a PWM handle for each entry in pwm-names
17 - vcc-supply: Phandle for the regulator supplying power
18 - direction-duty-cycle-ns: Duty cycle of the direction PWM channel in
26 pinctrl-single,pins = <
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/hwmon/ |
| D | npcm750-pwm-fan.txt | 1 Nuvoton NPCM7xx PWM and Fan Tacho controller device
3 The Nuvoton BMC NPCM7XX supports 8 Pulse-width modulation (PWM)
6 Required properties for pwm-fan node
7 - #address-cells : should be 1.
8 - #size-cells : should be 0.
9 - compatible : "nuvoton,npcm750-pwm-fan" for Poleg NPCM7XX.
10 - reg : specifies physical base address and size of the registers.
11 - reg-names : must contain:
12 * "pwm" for the PWM registers.
14 - clocks : phandle of reference clocks.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/hwmon/ |
| D | npcm750-pwm-fan.txt | 1 Nuvoton NPCM7xx PWM and Fan Tacho controller device
3 The Nuvoton BMC NPCM7XX supports 8 Pulse-width modulation (PWM)
6 Required properties for pwm-fan node
7 - #address-cells : should be 1.
8 - #size-cells : should be 0.
9 - compatible : "nuvoton,npcm750-pwm-fan" for Poleg NPCM7XX.
10 - reg : specifies physical base address and size of the registers.
11 - reg-names : must contain:
12 * "pwm" for the PWM registers.
14 - clocks : phandle of reference clocks.
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | rv1108.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/rv1108-cru.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 interrupt-parent = <&gic>;
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| D | stm32f429.dtsi | 2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include "armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
53 #address-cells = <1>;
54 #size-cells = <1>;
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | ingenic,tcu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 Documentation/mips/ingenic-tcu.rst.
14 - Paul Cercueil <paul@crapouillou.net>
21 - ingenic,jz4740-tcu
22 - ingenic,jz4725b-tcu
23 - ingenic,jz4770-tcu
24 - ingenic,jz4780-tcu
25 - ingenic,x1000-tcu
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