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3 The level-2 cache controller plays an important role in reducing memory latency7 reducing DRAM accesses.
8 every 64 bit word (effectively reducing available memory to 8/9).
15 * Simple wrappers reducing source bloat. Define all irq_stat fields
30 * WARNING: reducing MAX_WBITS makes minigzip unable to extract .gz files
9 reducing seek times. The size of a block group is specified in
12 reducing the total number of requests. This locality may also have the
16 Reducing this value will remove all label routing entries that
41 increase bandwidth over reducing interrupt rate.70 the algorithm: is it going left (reducing moderation), right (increasing
28 * that we have a single client waiting on each seqno, then reducing
39 of the chip is activated, reducing the supply current to 4uA.
23 Reducing this value will remove all label routing entries that
33 increase bandwidth over reducing interrupt rate.63 the algorithm: is it going left (reducing moderation), right (increasing
28 life can be extended by reducing the max battery charge
26 life can be extended by reducing the max battery charge
1 NO_HZ: Reducing Scheduling-Clock Ticks6 efficiency and reducing OS jitter. Reducing OS jitter is important for
38 by reducing the dury-cycle of pulses and not the current, which
37 by reducing the dury-cycle of pulses and not the current, which
72 * kernel page table mapping, reducing the size of the modules area.
26 * one extra instruction, but reducing register pressure will probably
2 NO_HZ: Reducing Scheduling-Clock Ticks8 efficiency and reducing OS jitter. Reducing OS jitter is important for