| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/ |
| D | mips-gic.txt | 4 It also supports local (per-processor) interrupts and software-generated
5 interrupts which can be used as IPIs. The GIC also includes a free-running
6 global timer, per-CPU count/compare timers, and a watchdog.
9 - compatible : Should be "mti,gic".
10 - interrupt-controller : Identifies the node as an interrupt controller
11 - #interrupt-cells : Specifies the number of cells needed to encode an
13 - The first cell is the type of interrupt, local or shared.
14 See <include/dt-bindings/interrupt-controller/mips-gic.h>.
15 - The second cell is the GIC interrupt number.
16 - The third cell encodes the interrupt flags.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | mti,gic.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Burton <paulburton@kernel.org>
11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
15 It also supports local (per-processor) interrupts and software-generated
16 interrupts which can be used as IPIs. The GIC also includes a free-running
17 global timer, per-CPU count/compare timers, and a watchdog.
23 "#interrupt-cells":
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| /kernel/linux/linux-5.10/arch/ia64/include/asm/ |
| D | hw_irq.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (C) 2001-2003 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
23 * 1,3-14 are reserved from firmware
25 * 16-255 (vectored external interrupts) are available
37 #define AUTO_ASSIGN -1
42 * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI.
45 #define IA64_CMCP_VECTOR 0x1d /* corrected machine-check polling vector */
47 #define IA64_CMC_VECTOR 0x1f /* corrected machine-check interrupt vector */
49 * Vectors 0x20-0x2f are reserved for legacy ISA IRQs.
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| /kernel/linux/linux-4.19/arch/ia64/include/asm/ |
| D | hw_irq.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (C) 2001-2003 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
24 * 1,3-14 are reserved from firmware
26 * 16-255 (vectored external interrupts) are available
38 #define AUTO_ASSIGN -1
43 * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI.
46 #define IA64_CMCP_VECTOR 0x1d /* corrected machine-check polling vector */
48 #define IA64_CMC_VECTOR 0x1f /* corrected machine-check interrupt vector */
50 * Vectors 0x20-0x2f are reserved for legacy ISA IRQs.
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| /kernel/linux/linux-5.10/arch/xtensa/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
47 Xtensa processors are 32-bit RISC machines designed by Tensilica
52 a home page at <http://www.linux-xtensa.org/>.
96 bool "fsf - default (not generic) configuration"
100 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
107 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
143 ie: it supports a TLB with auto-loading, page protection.
185 This option is used to indicate that the system-on-a-chip (SOC)
187 the CPU core definition and currently needs to be selected manually.
199 bool "Enable Symmetric multi-processing support"
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|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/powerpc/ |
| D | ibm,powerpc-cpu-features.txt | 3 (skiboot/doc/device-tree/ibm,powerpc-cpu-features/binding.txt)
9 ibm,powerpc-cpu-features binding
12 This device tree binding describes CPU features available to software, with
19 /cpus/ibm,powerpc-cpu-features node binding
20 -------------------------------------------
22 Node: ibm,powerpc-cpu-features
24 Description: Container of CPU feature nodes.
26 The node name must be "ibm,powerpc-cpu-features".
35 - compatible
38 Definition: "ibm,powerpc-cpu-features"
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/ |
| D | ibm,powerpc-cpu-features.txt | 3 (skiboot/doc/device-tree/ibm,powerpc-cpu-features/binding.txt)
9 ibm,powerpc-cpu-features binding
12 This device tree binding describes CPU features available to software, with
19 /cpus/ibm,powerpc-cpu-features node binding
20 -------------------------------------------
22 Node: ibm,powerpc-cpu-features
24 Description: Container of CPU feature nodes.
26 The node name must be "ibm,powerpc-cpu-features".
35 - compatible
38 Definition: "ibm,powerpc-cpu-features"
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|
| /kernel/linux/linux-4.19/arch/m68k/ |
| D | Kconfig.machine | 1 # SPDX-License-Identifier: GPL-2.0
20 This option enables support for the 68000-based Atari series of
42 Say Y here if you want to run Linux on an MC680x0-based Apollo
61 build a kernel which can run on MVME147 single-board computers. If
116 The Q40 is a Motorola 68040-based successor to the Sinclair QL
119 Q60. Select your CPU below. For 68LC060 don't forget to enable FPU
176 Disable the CPU internal registers protection in user mode,
267 Support for the Sysam AMCORE open-hardware generic board.
273 Support for the Sysam stmark2 open-hardware generic board.
306 bool "Netburner MOD-5272 board support"
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| /kernel/linux/linux-5.10/arch/m68k/ |
| D | Kconfig.machine | 1 # SPDX-License-Identifier: GPL-2.0
21 This option enables support for the 68000-based Atari series of
47 Say Y here if you want to run Linux on an MC680x0-based Apollo
66 build a kernel which can run on MVME147 single-board computers. If
121 The Q40 is a Motorola 68040-based successor to the Sinclair QL
124 Q60. Select your CPU below. For 68LC060 don't forget to enable FPU
182 Disable the CPU internal registers protection in user mode,
273 Support for the Sysam AMCORE open-hardware generic board.
279 Support for the Sysam stmark2 open-hardware generic board.
312 bool "Netburner MOD-5272 board support"
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| /kernel/linux/linux-4.19/drivers/irqchip/ |
| D | irq-mips-gic.c | 6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
10 #define pr_fmt(fmt) "irq-mips-gic: " fmt
24 #include <asm/mips-cps.h>
28 #include <dt-bindings/interrupt-controller/mips-gic.h>
33 /* Add 2 to convert GIC CPU pin to core interrupt */
42 #define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
45 #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
102 irq -= GIC_PIN_TO_VEC_OFFSET; in gic_bind_eic_interrupt()
108 static void gic_send_ipi(struct irq_data *d, unsigned int cpu) in gic_send_ipi() argument
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| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-mips-gic.c | 6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
10 #define pr_fmt(fmt) "irq-mips-gic: " fmt
24 #include <asm/mips-cps.h>
28 #include <dt-bindings/interrupt-controller/mips-gic.h>
33 /* Add 2 to convert GIC CPU pin to core interrupt */
42 #define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
45 #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
102 irq -= GIC_PIN_TO_VEC_OFFSET; in gic_bind_eic_interrupt()
108 static void gic_send_ipi(struct irq_data *d, unsigned int cpu) in gic_send_ipi() argument
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| /kernel/linux/linux-4.19/arch/xtensa/include/asm/ |
| D | mmu_context.h | 8 * Copyright (C) 2001 - 2013 Tensilica Inc.
22 #include <asm/vectors.h>
27 #include <asm-generic/mm_hooks.h>
28 #include <asm-generic/percpu.h>
35 #define cpu_asid_cache(cpu) per_cpu(asid_cache, cpu) argument
39 * any user or kernel context. We use the reserved values in the
44 * 2 reserved
45 * 3 reserved
51 #define ASID_MASK ((1 << XCHAL_MMU_ASID_BITS) - 1)
70 static inline void get_new_mmu_context(struct mm_struct *mm, unsigned int cpu) in get_new_mmu_context() argument
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| /kernel/linux/linux-5.10/arch/xtensa/include/asm/ |
| D | mmu_context.h | 8 * Copyright (C) 2001 - 2013 Tensilica Inc.
23 #include <asm/vectors.h>
27 #include <asm-generic/mm_hooks.h>
28 #include <asm-generic/percpu.h>
35 #define cpu_asid_cache(cpu) per_cpu(asid_cache, cpu) argument
39 * any user or kernel context. We use the reserved values in the
44 * 2 reserved
45 * 3 reserved
51 #define ASID_MASK ((1 << XCHAL_MMU_ASID_BITS) - 1)
70 static inline void get_new_mmu_context(struct mm_struct *mm, unsigned int cpu) in get_new_mmu_context() argument
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| /kernel/linux/linux-4.19/kernel/irq/ |
| D | matrix.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/cpu.h>
43 * irq_alloc_matrix - Allocate a irq_matrix structure and initialize it
62 m->matrix_bits = matrix_bits; in irq_alloc_matrix()
63 m->alloc_start = alloc_start; in irq_alloc_matrix()
64 m->alloc_end = alloc_end; in irq_alloc_matrix()
65 m->alloc_size = alloc_end - alloc_start; in irq_alloc_matrix()
66 m->maps = alloc_percpu(*m->maps); in irq_alloc_matrix()
67 if (!m->maps) { in irq_alloc_matrix()
75 * irq_matrix_online - Bring the local CPU matrix online
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| /kernel/linux/linux-5.10/kernel/irq/ |
| D | matrix.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/cpu.h>
43 * irq_alloc_matrix - Allocate a irq_matrix structure and initialize it
62 m->matrix_bits = matrix_bits; in irq_alloc_matrix()
63 m->alloc_start = alloc_start; in irq_alloc_matrix()
64 m->alloc_end = alloc_end; in irq_alloc_matrix()
65 m->alloc_size = alloc_end - alloc_start; in irq_alloc_matrix()
66 m->maps = alloc_percpu(*m->maps); in irq_alloc_matrix()
67 if (!m->maps) { in irq_alloc_matrix()
75 * irq_matrix_online - Bring the local CPU matrix online
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| /kernel/linux/linux-5.10/arch/x86/kernel/apic/ |
| D | vector.c | 1 // SPDX-License-Identifier: GPL-2.0-only
30 unsigned int cpu; member
67 info->mask = mask; in init_irq_alloc_info()
83 while (irqd->parent_data) in apic_chip_data()
84 irqd = irqd->parent_data; in apic_chip_data()
86 return irqd->chip_data; in apic_chip_data()
93 return apicd ? &apicd->hw_irq_cfg : NULL; in irqd_cfg()
108 INIT_HLIST_NODE(&apicd->clist); in alloc_apic_chip_data()
118 unsigned int cpu) in apic_update_irq_cfg() argument
124 apicd->hw_irq_cfg.vector = vector; in apic_update_irq_cfg()
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| /kernel/linux/linux-4.19/arch/x86/kernel/apic/ |
| D | vector.c | 32 unsigned int cpu; member
69 info->mask = mask; in init_irq_alloc_info()
85 while (irqd->parent_data) in apic_chip_data()
86 irqd = irqd->parent_data; in apic_chip_data()
88 return irqd->chip_data; in apic_chip_data()
95 return apicd ? &apicd->hw_irq_cfg : NULL; in irqd_cfg()
110 INIT_HLIST_NODE(&apicd->clist); in alloc_apic_chip_data()
120 unsigned int cpu) in apic_update_irq_cfg() argument
126 apicd->hw_irq_cfg.vector = vector; in apic_update_irq_cfg()
127 apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu); in apic_update_irq_cfg()
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|
| /kernel/linux/linux-4.19/Documentation/arm/ |
| D | memory.txt | 10 The ARM CPU is capable of addressing a maximum of 4GB virtual memory
19 --------------------------------------------------------------------------
26 ffff1000 ffff7fff Reserved.
29 ffff0000 ffff0fff CPU vector page.
30 The CPU vectors are mapped here if the
31 CPU supports vector relocation (control
35 in proc-xscale.S to flush the whole data
39 DTCM mounted inside the CPU.
42 ITCM mounted inside the CPU.
50 VMALLOC_START VMALLOC_END-1 vmalloc() / ioremap() space.
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| /kernel/linux/linux-5.10/Documentation/arm/ |
| D | memory.rst | 13 The ARM CPU is capable of addressing a maximum of 4GB virtual memory
30 ffff1000 ffff7fff Reserved.
33 ffff0000 ffff0fff CPU vector page.
34 The CPU vectors are mapped here if the
35 CPU supports vector relocation (control
39 in proc-xscale.S to flush the whole data
43 DTCM mounted inside the CPU.
46 ITCM mounted inside the CPU.
53 ff800000 ffbfffff Permanent, fixed read-only mapping of the
59 VMALLOC_START VMALLOC_END-1 vmalloc() / ioremap() space.
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| /kernel/linux/linux-4.19/arch/xtensa/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
41 Xtensa processors are 32-bit RISC machines designed by Tensilica
46 a home page at <http://www.linux-xtensa.org/>.
93 bool "fsf - default (not generic) configuration"
97 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
104 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
140 ie: it supports a TLB with auto-loading, page protection.
182 This option is use to indicate that the system-on-a-chip (SOC)
184 the CPU core definition and currently needs to be selected manually.
196 bool "Enable Symmetric multi-processing support"
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|
| /kernel/linux/linux-5.10/arch/arc/kernel/ |
| D | entry-arcv2.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling
16 ; first 16 lines are reserved for exceptions and are not configurable.
19 .cpu HS
28 # Initial 16 slots are Exception Vectors
43 VECTOR reserved ; Reserved slots
44 VECTOR reserved ; Reserved slots
46 # Begin Interrupt Vectors
57 .rept NR_CPU_IRQS - 8
63 reserved: label
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| /kernel/liteos_a/arch/arm/arm/src/startup/ |
| D | reset_vector_up.S | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
61 .fpu neon-vfpv4
63 .arch armv7-a
66 /* param0 is stack bottom, param1 is stack size, r11 hold cpu id */
82 .section ".vectors","ax"
86 *Assumption: ROM code has these vectors at the hardware reset address.
87 *A simple jump removes any address-space dependencies [i.e. safer]
102 /* do some early cpu setup: i/d cache disable, mmu disabled */
155 bl memset_optimized /* optimized memset since r0 is 64-byte aligned */
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| D | reset_vector_mp.S | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
63 .fpu neon-vfpv4
65 .arch armv7-a
68 /* param0 is stack bottom, param1 is stack size, r12 hold cpu id */
84 .section ".vectors","ax"
89 *Assumption: ROM code has these vectors at the hardware reset address.
90 *A simple jump removes any address-space dependencies [i.e. safer]
122 /* do some early cpu setup: i/d cache disable, mmu disabled */
180 bl memset_optimized /* optimized memset since r0 is 64-byte aligned */
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| /kernel/linux/linux-4.19/arch/arc/kernel/ |
| D | entry-arcv2.S | 2 * ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling
19 ; first 16 lines are reserved for exceptions and are not configurable.
22 .cpu HS
31 # Initial 16 slots are Exception Vectors
46 VECTOR reserved ; Reserved slots
47 VECTOR reserved ; Reserved slots
49 # Begin Interrupt Vectors
60 .rept NR_CPU_IRQS - 8
66 reserved: label
83 # Note this disable is only for consistent book-keeping as further interrupts
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| /kernel/linux/linux-4.19/Documentation/filesystems/ |
| D | xfs-delayed-logging-design.txt | 2 --------------------------
4 Introduction to Re-logging in XFS
5 ---------------------------------
9 logged are made up of the changes to in-core structures rather than on-disk
10 structures. Other objects - typically buffers - have their physical changes
21 "re-logging". Conceptually, this is quite simple - all it requires is that any
45 (increasing) LSN of each subsequent transaction - the LSN is effectively a
48 This relogging is also used to implement long-running, multiple-commit
62 the log - repeated operations to the same objects write the same changes to
71 doing aggregation of transactions in memory - batching them, if you like - to
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|