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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/rtc/
Dingenic,jz4740-rtc.txt1 JZ4740 and similar SoCs real-time clock driver
5 - compatible: One of:
6 - "ingenic,jz4740-rtc" - for use with the JZ4740 SoC
7 - "ingenic,jz4780-rtc" - for use with the JZ4780 SoC
8 - reg: Address range of rtc register set
9 - interrupts: IRQ number for the alarm interrupt
10 - clocks: phandle to the "rtc" clock
11 - clock-names: must be "rtc"
14 - system-power-controller: To use this component as the
16 - reset-pin-assert-time-ms: Reset pin low-level assertion
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/rtc/
Dingenic,rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs Real-Time Clock DT bindings
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: rtc.yaml#
18 - enum:
19 - ingenic,jz4740-rtc
20 - ingenic,jz4760-rtc
21 - items:
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dintel-gw-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dilip Kota <eswara.kota@linux.intel.com>
16 const: intel,lgm-pcie
18 - compatible
23 - const: intel,lgm-pcie
24 - const: snps,dw-pcie
29 "#address-cells":
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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/sound/
Dti,tas5086.txt1 Texas Instruments TAS5086 6-channel PWM Processor
5 - compatible: Should contain "ti,tas5086".
6 - reg: The i2c address. Should contain <0x1b>.
10 - reset-gpio: A GPIO spec to define which pin is connected to the
11 chip's !RESET pin. If specified, the driver will
12 assert a hardware reset at probe time.
14 - ti,charge-period: This property should contain the time in microseconds
15 that closely matches the external single-ended
16 split-capacitor charge period. The hardware chip
20 When not specified, the hardware default of 1300ms
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/
Dti,tas5086.txt1 Texas Instruments TAS5086 6-channel PWM Processor
5 - compatible: Should contain "ti,tas5086".
6 - reg: The i2c address. Should contain <0x1b>.
10 - reset-gpio: A GPIO spec to define which pin is connected to the
11 chip's !RESET pin. If specified, the driver will
12 assert a hardware reset at probe time.
14 - ti,charge-period: This property should contain the time in microseconds
15 that closely matches the external single-ended
16 split-capacitor charge period. The hardware chip
20 When not specified, the hardware default of 1300ms
[all …]
/kernel/linux/linux-5.10/drivers/scsi/
Dmesh.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
5 * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
11 * Apr. 21 2002 - BenH Rework bus reset code for new error handler
12 * Add delay after initial bus reset
15 * Sep. 27 2003 - BenH Move to new driver model, fix some write posting
18 * - handle aborts correctly
19 * - retry arbitration if lost (unless higher levels do this for us)
20 * - power down the chip when no device is detected
76 MODULE_PARM_DESC(init_reset_delay, "Initial bus reset delay (0=no reset)");
[all …]
Dmesh.h1 /* SPDX-License-Identifier: GPL-2.0 */
53 #define SEQ_ATN 0x20 /* assert ATN signal */
69 #define SEQ_RESETMESH 0x0e /* reset the controller */
103 #define ERR_SCSIRESET 0x20 /* SCSI bus got reset on us */
124 * The units of the sel_timeout register are 10ms.
/kernel/linux/linux-4.19/drivers/scsi/
Dmesh.c2 * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
4 * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
10 * Apr. 21 2002 - BenH Rework bus reset code for new error handler
11 * Add delay after initial bus reset
14 * Sep. 27 2003 - BenH Move to new driver model, fix some write posting
17 * - handle aborts correctly
18 * - retry arbitration if lost (unless higher levels do this for us)
19 * - power down the chip when no device is detected
75 MODULE_PARM_DESC(init_reset_delay, "Initial bus reset delay (0=no reset)");
84 #define DEBUG_TARGET(cmd) ((cmd) && ALLOW_DEBUG((cmd)->device->id))
[all …]
Dmesh.h1 /* SPDX-License-Identifier: GPL-2.0 */
53 #define SEQ_ATN 0x20 /* assert ATN signal */
69 #define SEQ_RESETMESH 0x0e /* reset the controller */
103 #define ERR_SCSIRESET 0x20 /* SCSI bus got reset on us */
124 * The units of the sel_timeout register are 10ms.
/kernel/linux/linux-5.10/drivers/rtc/
Drtc-jz4740.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
66 return readl(rtc->base + reg); in jz4740_rtc_reg_read()
76 } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout); in jz4740_rtc_wait_write_ready()
78 return timeout ? 0 : -EIO; in jz4740_rtc_wait_write_ready()
90 writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
93 ctrl = readl(rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
94 } while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout); in jz4780_rtc_enable_write()
96 return timeout ? 0 : -EIO; in jz4780_rtc_enable_write()
104 if (rtc->type >= ID_JZ4760) in jz4740_rtc_reg_write()
[all …]
/kernel/linux/linux-4.19/drivers/rtc/
Drtc-jz4740.c2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
79 return readl(rtc->base + reg); in jz4740_rtc_reg_read()
89 } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout); in jz4740_rtc_wait_write_ready()
91 return timeout ? 0 : -EIO; in jz4740_rtc_wait_write_ready()
103 writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
106 ctrl = readl(rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
107 } while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout); in jz4780_rtc_enable_write()
109 return timeout ? 0 : -EIO; in jz4780_rtc_enable_write()
117 if (rtc->type >= ID_JZ4780) in jz4740_rtc_reg_write()
122 writel(val, rtc->base + reg); in jz4740_rtc_reg_write()
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/kernel/linux/linux-5.10/drivers/net/wireless/intersil/orinoco/
Dorinoco_pci.c4 * (i.e. these are not PCMCIA cards in a PCMCIA-to-PCI bridge).
14 * Some of this code is "inspired" by linux-wlan-ng-0.1.10, but nothing
15 * has been copied from it. linux-wlan-ng-0.1.10 is originally :
20 * (C) Copyright David Gibson, IBM Corp. 2002-2003.
59 /* Bitmask to reset the card */
62 /* Magic timeouts for doing the reset.
63 * Those times are straight from wlan-ng, and it is claimed that they
65 #define HERMES_PCI_COR_ONT (250) /* ms */
66 #define HERMES_PCI_COR_OFFT (500) /* ms */
67 #define HERMES_PCI_COR_BUSYT (500) /* ms */
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/kernel/linux/linux-4.19/drivers/net/wireless/intersil/orinoco/
Dorinoco_pci.c4 * (i.e. these are not PCMCIA cards in a PCMCIA-to-PCI bridge).
14 * Some of this code is "inspired" by linux-wlan-ng-0.1.10, but nothing
15 * has been copied from it. linux-wlan-ng-0.1.10 is originally :
20 * (C) Copyright David Gibson, IBM Corp. 2002-2003.
59 /* Bitmask to reset the card */
62 /* Magic timeouts for doing the reset.
63 * Those times are straight from wlan-ng, and it is claimed that they
65 #define HERMES_PCI_COR_ONT (250) /* ms */
66 #define HERMES_PCI_COR_OFFT (500) /* ms */
67 #define HERMES_PCI_COR_BUSYT (500) /* ms */
[all …]
/kernel/linux/linux-5.10/drivers/macintosh/
Dmediabay.c1 // SPDX-License-Identifier: GPL-2.0-or-later
32 #define MB_FCR32(bay, r) ((bay)->base + ((r) >> 2))
33 #define MB_FCR8(bay, r) (((volatile u8 __iomem *)((bay)->base)) + (r))
76 * Wait that number of ms between each step in normal polling mode
81 * Consider the media-bay ID value stable if it is the same for
86 /* Wait after powering up the media bay this delay in ms
92 * Hold the media-bay reset signal true for this many ticks
98 * Wait this long after the reset signal is released and before doing
99 * further operations. After this delay, the IDE reset signal is released
105 * Wait this many ticks after an IDE device (e.g. CD-ROM) is inserted
[all …]
/kernel/linux/linux-4.19/drivers/macintosh/
Dmediabay.c36 #define MB_FCR32(bay, r) ((bay)->base + ((r) >> 2))
37 #define MB_FCR8(bay, r) (((volatile u8 __iomem *)((bay)->base)) + (r))
80 * Wait that number of ms between each step in normal polling mode
85 * Consider the media-bay ID value stable if it is the same for
90 /* Wait after powering up the media bay this delay in ms
96 * Hold the media-bay reset signal true for this many ticks
102 * Wait this long after the reset signal is released and before doing
103 * further operations. After this delay, the IDE reset signal is released
109 * Wait this many ticks after an IDE device (e.g. CD-ROM) is inserted
121 mb_resetting, /* reset bit unset, waiting MB_SETUP_DELAY */
[all …]
/kernel/linux/linux-5.10/drivers/phy/ralink/
Dphy-ralink-usb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include <linux/reset.h>
63 writel(val, phy->base + reg); in u2_phy_w32()
68 return readl(phy->base + reg); in u2_phy_r32()
97 regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1, in ralink_usb_phy_power_on()
98 phy->clk, phy->clk); in ralink_usb_phy_power_on()
101 regmap_update_bits(phy->sysctl, RT_SYSC_REG_SYSCFG1, in ralink_usb_phy_power_on()
105 /* deassert the reset lines */ in ralink_usb_phy_power_on()
106 reset_control_deassert(phy->rsthost); in ralink_usb_phy_power_on()
107 reset_control_deassert(phy->rstdev); in ralink_usb_phy_power_on()
[all …]
/kernel/linux/linux-4.19/drivers/phy/ralink/
Dphy-ralink-usb.c29 #include <linux/reset.h>
72 writel(val, phy->base + reg); in u2_phy_w32()
77 return readl(phy->base + reg); in u2_phy_r32()
106 regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1, in ralink_usb_phy_power_on()
107 phy->clk, phy->clk); in ralink_usb_phy_power_on()
110 regmap_update_bits(phy->sysctl, RT_SYSC_REG_SYSCFG1, in ralink_usb_phy_power_on()
114 /* deassert the reset lines */ in ralink_usb_phy_power_on()
115 reset_control_deassert(phy->rsthost); in ralink_usb_phy_power_on()
116 reset_control_deassert(phy->rstdev); in ralink_usb_phy_power_on()
119 * The SDK kernel had a delay of 100ms. however on device in ralink_usb_phy_power_on()
[all …]
/kernel/linux/linux-5.10/drivers/pps/clients/
Dpps-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pps-gpio.c -- PPS client driver using GPIO
9 #define PPS_GPIO_NAME "pps-gpio"
19 #include <linux/pps-gpio.h>
34 struct timer_list echo_timer; /* timer to reset echo active state */
56 rising_edge = gpiod_get_value(info->gpio_pin); in pps_gpio_irq_handler()
57 if ((rising_edge && !info->assert_falling_edge) || in pps_gpio_irq_handler()
58 (!rising_edge && info->assert_falling_edge)) in pps_gpio_irq_handler()
59 pps_event(info->pps, &ts, PPS_CAPTUREASSERT, data); in pps_gpio_irq_handler()
60 else if (info->capture_clear && in pps_gpio_irq_handler()
[all …]
/kernel/linux/linux-4.19/drivers/watchdog/
Dpnx4008_wdt.c11 * 2005-2006 (c) MontaVista Software, Inc.
38 /* WatchDog Timer - Chapter 23 Page 207 */
91 /* stop counter, initiate counter reset */ in pnx4008_wdt_start()
93 /*wait for reset to complete. 100% guarantee event */ in pnx4008_wdt_start()
96 /* internal and external reset, stop after that */ in pnx4008_wdt_start()
102 /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */ in pnx4008_wdt_start()
104 writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base)); in pnx4008_wdt_start()
125 wdd->timeout = new_timeout; in pnx4008_wdt_set_timeout()
137 * - For details, see the 'reboot' syscall in kernel/reboot.c in pnx4008_restart_handler()
138 * - If the received "cmd" is not supported, use the default mode. in pnx4008_restart_handler()
[all …]
/kernel/linux/linux-5.10/drivers/watchdog/
Dpnx4008_wdt.c1 // SPDX-License-Identifier: GPL-2.0
12 * 2005-2006 (c) MontaVista Software, Inc.
34 /* WatchDog Timer - Chapter 23 Page 207 */
87 /* stop counter, initiate counter reset */ in pnx4008_wdt_start()
89 /*wait for reset to complete. 100% guarantee event */ in pnx4008_wdt_start()
92 /* internal and external reset, stop after that */ in pnx4008_wdt_start()
98 /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */ in pnx4008_wdt_start()
100 writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base)); in pnx4008_wdt_start()
121 wdd->timeout = new_timeout; in pnx4008_wdt_set_timeout()
133 * - For details, see the 'reboot' syscall in kernel/reboot.c in pnx4008_restart_handler()
[all …]
/kernel/linux/linux-5.10/include/linux/
Drmi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2011-2016 Synaptics Incorporated
21 * struct rmi_2d_axis_alignment - target axis alignment
22 * @swap_axes: set to TRUE if desired to swap x- and y-axis
23 * @flip_x: set to TRUE if desired to flip direction on x-axis
24 * @flip_y: set to TRUE if desired to flip direction on y-axis
25 * @clip_x_low - reported X coordinates below this setting will be clipped to
27 * @clip_x_high - reported X coordinates above this setting will be clipped to
29 * @clip_y_low - reported Y coordinates below this setting will be clipped to
31 * @clip_y_high - reported Y coordinates above this setting will be clipped to
[all …]
/kernel/linux/linux-4.19/include/linux/
Drmi.h2 * Copyright (c) 2011-2016 Synaptics Incorporated
24 * struct rmi_2d_axis_alignment - target axis alignment
25 * @swap_axes: set to TRUE if desired to swap x- and y-axis
26 * @flip_x: set to TRUE if desired to flip direction on x-axis
27 * @flip_y: set to TRUE if desired to flip direction on y-axis
28 * @clip_x_low - reported X coordinates below this setting will be clipped to
30 * @clip_x_high - reported X coordinates above this setting will be clipped to
32 * @clip_y_low - reported Y coordinates below this setting will be clipped to
34 * @clip_y_high - reported Y coordinates above this setting will be clipped to
36 * @offset_x - this value will be added to all reported X coordinates
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/rockchip/
Drk3399-gru-scarlet.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-scarlet board device tree source
8 #include "rk3399-gru.dtsi"
14 pp1250_s3: pp1250-s3 {
15 compatible = "regulator-fixed";
16 regulator-name = "pp1250_s3";
19 regulator-always-on;
20 regulator-boot-on;
21 regulator-min-microvolt = <1250000>;
22 regulator-max-microvolt = <1250000>;
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/chelsio/cxgb/
Dpm3393.c7 * PMC/SIERRA (pm3393) MAC-PHY functionality. *
23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
96 t1_tpi_read(cmac->adapter, OFFSET(reg), data32); in pmread()
102 t1_tpi_write(cmac->adapter, OFFSET(reg), data32); in pmwrite()
106 /* Port reset. */
124 /* PM3393 - Enabling all hardware block interrupts. in pm3393_interrupt_enable()
147 /* PM3393 - Global interrupt enable in pm3393_interrupt_enable()
153 /* TERMINATOR - PL_INTERUPTS_EXT */ in pm3393_interrupt_enable()
154 pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE); in pm3393_interrupt_enable()
156 writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE); in pm3393_interrupt_enable()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/chelsio/cxgb/
Dpm3393.c7 * PMC/SIERRA (pm3393) MAC-PHY functionality. *
23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
96 t1_tpi_read(cmac->adapter, OFFSET(reg), data32); in pmread()
102 t1_tpi_write(cmac->adapter, OFFSET(reg), data32); in pmwrite()
106 /* Port reset. */
124 /* PM3393 - Enabling all hardware block interrupts. in pm3393_interrupt_enable()
147 /* PM3393 - Global interrupt enable in pm3393_interrupt_enable()
153 /* TERMINATOR - PL_INTERUPTS_EXT */ in pm3393_interrupt_enable()
154 pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE); in pm3393_interrupt_enable()
156 writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE); in pm3393_interrupt_enable()
[all …]

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