| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | mdio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
17 bus. These should follow the generic ethernet-phy.yaml document, or
24 "#address-cells":
27 "#size-cells":
30 reset-gpios:
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| D | ethernet-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
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| D | fsl-fec.txt | 4 - compatible : Should be "fsl,<soc>-fec"
5 - reg : Address and length of the register set for the device
6 - interrupts : Should contain fec interrupt
7 - phy-mode : See ethernet.txt file in the same directory
10 - phy-supply : regulator that powers the Ethernet PHY.
11 - phy-handle : phandle to the PHY device connected to this device.
12 - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
13 Use instead of phy-handle.
14 - fsl,num-tx-queues : The property is valid for enet-avb IP, which supports
17 - fsl,num-rx-queues : The property is valid for enet-avb IP, which supports
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/power/reset/ |
| D | gpio-restart.txt | 4 This binding supports level and edge triggered reset. At driver load
6 handler. If the optional properties 'open-source' is not found, the GPIO line
12 triggering a level triggered reset condition. This will also cause an
13 inactive->active edge condition, triggering positive edge triggered
14 reset. After a delay specified by active-delay, the GPIO is set to
15 inactive, thus causing an active->inactive edge, triggering negative edge
16 triggered reset. After a delay specified by inactive-delay, the GPIO
17 is driven active again. After a delay specified by wait-delay, the
21 - compatible : should be "gpio-restart".
22 - gpios : The GPIO to set high/low, see "gpios property" in
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/reset/ |
| D | gpio-restart.txt | 4 This binding supports level and edge triggered reset. At driver load
6 handler. If the optional properties 'open-source' is not found, the GPIO line
12 triggering a level triggered reset condition. This will also cause an
13 inactive->active edge condition, triggering positive edge triggered
14 reset. After a delay specified by active-delay, the GPIO is set to
15 inactive, thus causing an active->inactive edge, triggering negative edge
16 triggered reset. After a delay specified by inactive-delay, the GPIO
17 is driven active again. After a delay specified by wait-delay, the
21 - compatible : should be "gpio-restart".
22 - gpios : The GPIO to set high/low, see "gpios property" in
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/panel/ |
| D | samsung,s6e8aa0.txt | 4 - compatible: "samsung,s6e8aa0"
5 - reg: the virtual channel number of a DSI peripheral
6 - vdd3-supply: core voltage supply
7 - vci-supply: voltage supply for analog circuits
8 - reset-gpios: a GPIO spec for the reset pin
9 - display-timings: timings for the connected panel as described by [1]
12 - power-on-delay: delay after turning regulators on [ms]
13 - reset-delay: delay after reset sequence [ms]
14 - init-delay: delay after initialization sequence [ms]
15 - panel-width-mm: physical panel width [mm]
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| D | samsung,ld9040.txt | 4 - compatible: "samsung,ld9040"
5 - reg: address of the panel on SPI bus
6 - vdd3-supply: core voltage supply
7 - vci-supply: voltage supply for analog circuits
8 - reset-gpios: a GPIO spec for the reset pin
9 - display-timings: timings for the connected panel according to [1]
14 - power-on-delay: delay after turning regulators on [ms]
15 - reset-delay: delay after reset sequence [ms]
16 - panel-width-mm: physical panel width [mm]
17 - panel-height-mm: physical panel height [mm]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/panel/ |
| D | samsung,s6e8aa0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrzej Hajda <a.hajda@samsung.com>
13 - $ref: panel-common.yaml#
20 reset-gpios: true
21 display-timings: true
23 vdd3-supply:
26 vci-supply:
29 power-on-delay:
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| D | samsung,ld9040.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 spi/spi-controller.yaml
14 - Andrzej Hajda <a.hajda@samsung.com>
17 - $ref: panel-common.yaml#
23 display-timings: true
26 reset-gpios: true
28 vdd3-supply:
31 vci-supply:
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/ |
| D | fsl-fec.txt | 4 - compatible : Should be "fsl,<soc>-fec"
5 - reg : Address and length of the register set for the device
6 - interrupts : Should contain fec interrupt
7 - phy-mode : See ethernet.txt file in the same directory
10 - phy-reset-gpios : Should specify the gpio for phy reset
11 - phy-reset-duration : Reset duration in milliseconds. Should present
12 only if property "phy-reset-gpios" is available. Missing the property
15 - phy-reset-active-high : If present then the reset sequence using the GPIO
16 specified in the "phy-reset-gpios" property is reversed (H=reset state,
18 - phy-reset-post-delay : Post reset delay in milliseconds. If present then
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| D | mdio.txt | 6 - reset-gpios: One GPIO that control the RESET lines of all PHYs on that MDIO
8 - reset-delay-us: RESET pulse width in microseconds.
13 The 'reset-delay-us' indicates the RESET signal pulse width in microseconds and
15 on all PHY requirements (maximum value of all per-PHY RESET pulse widths).
24 #address-cells = <1>;
25 #size-cells = <0>;
27 reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
28 reset-delay-us = <2>;
30 ethphy0: ethernet-phy@1 {
34 ethphy1: ethernet-phy@3 {
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| D | phy.txt | 5 - interrupts : interrupt specifier for the sole interrupt.
6 - reg : The ID number for the phy, usually a small integer
10 - compatible: Compatible list, may contain
11 "ethernet-phy-ieee802.3-c22" or "ethernet-phy-ieee802.3-c45" for
18 form: "ethernet-phy-idAAAA.BBBB" where
19 AAAA - The value of the 16 bit Phy Identifier 1 register as
21 BBBB - The value of the 16 bit Phy Identifier 2 register as
28 - max-speed: Maximum PHY supported speed (10, 100, 1000...)
30 - broken-turn-around: If set, indicates the PHY device does not correctly
33 - enet-phy-lane-swap: If set, indicates the PHY will swap the TX/RX lanes to
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| /kernel/linux/linux-5.10/include/linux/reset/ |
| D | reset-simple.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Simple Reset Controller ops
5 * Based on Allwinner SoCs Reset Controller driver
9 * Maxime Ripard <maxime.ripard@free-electrons.com>
16 #include <linux/reset-controller.h>
20 * struct reset_simple_data - driver data for simple reset controllers
21 * @lock: spinlock to protect registers during read-modify-write cycles
23 * @rcdev: reset controller device base structure
24 * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits
25 * are set to assert the reset. Note that this says nothing about
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/c6x/ |
| D | clocks.txt | 2 -------------------------
4 This is a first-cut support for the SoC clock controllers. This is still
10 - compatible: "ti,c64x+pll"
11 May also have SoC-specific value to support SoC-specific initialization
13 "ti,c6455-pll"
14 "ti,c6457-pll"
15 "ti,c6472-pll"
16 "ti,c6474-pll"
18 - reg: base address and size of register area
19 - clock-frequency: input clock frequency in hz
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/c6x/ |
| D | clocks.txt | 2 -------------------------
4 This is a first-cut support for the SoC clock controllers. This is still
10 - compatible: "ti,c64x+pll"
11 May also have SoC-specific value to support SoC-specific initialization
13 "ti,c6455-pll"
14 "ti,c6457-pll"
15 "ti,c6472-pll"
16 "ti,c6474-pll"
18 - reg: base address and size of register area
19 - clock-frequency: input clock frequency in hz
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | cadence-quadspi.txt | 4 - compatible : should be one of the following:
5 Generic default - "cdns,qspi-nor".
6 For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
7 For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
8 - reg : Contains two entries, each of which is a tuple consisting of a
12 - interrupts : Unit interrupt specifier for the controller interrupt.
13 - clocks : phandle to the Quad SPI clock.
14 - cdns,fifo-depth : Size of the data FIFO in words.
15 - cdns,fifo-width : Bus width of the data FIFO in bytes.
16 - cdns,trigger-address : 32-bit indirect AHB trigger address.
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mmc/ |
| D | mmc-pwrseq-simple.txt | 8 - compatible : contains "mmc-pwrseq-simple".
11 - reset-gpios : contains a list of GPIO specifiers. The reset GPIOs are asserted
13 They will be de-asserted right after the power has been provided to the
15 - clocks : Must contain an entry for the entry in clock-names.
16 See ../clocks/clock-bindings.txt for details.
17 - clock-names : Must include the following entry:
19 - post-power-on-delay-ms : Delay in ms after powering the card and
20 de-asserting the reset-gpios (if any)
21 - power-off-delay-us : Delay in us after asserting the reset-gpios (if any)
27 compatible = "mmc-pwrseq-simple";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/input/ |
| D | nvidia,tegra20-kbc.txt | 7 - compatible: "nvidia,tegra20-kbc"
8 - reg: Register base address of KBC.
9 - interrupts: Interrupt number for the KBC.
10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
14 - linux,keymap: The keymap for keys as described in the binding document
15 devicetree/bindings/input/matrix-keymap.txt.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/input/ |
| D | nvidia,tegra20-kbc.txt | 7 - compatible: "nvidia,tegra20-kbc"
8 - reg: Register base address of KBC.
9 - interrupts: Interrupt number for the KBC.
10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
14 - linux,keymap: The keymap for keys as described in the binding document
15 devicetree/bindings/input/matrix-keymap.txt.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | mmc-pwrseq-simple.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
19 const: mmc-pwrseq-simple
21 reset-gpios:
26 contains a list of GPIO specifiers. The reset GPIOs are asserted
28 They will be de-asserted right after the power has been provided to the
33 description: Handle for the entry in clock-names.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/ |
| D | nvidia,tegra114-spi.txt | 4 - compatible : For Tegra114, must contain "nvidia,tegra114-spi".
5 Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where
7 - reg: Should contain SPI registers location and length.
8 - interrupts: Should contain SPI interrupts.
9 - clock-names : Must include the following entries:
10 - spi
11 - resets : Must contain an entry for each entry in reset-names.
12 See ../reset/reset.txt for details.
13 - reset-names : Must include the following entries:
14 - spi
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| /kernel/linux/linux-5.10/include/linux/dma/ |
| D | xilinx_dma.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
11 #include <linux/dma-mapping.h>
15 * struct xilinx_vdma_config - VDMA Configuration structure
16 * @frm_dly: Frame delay
17 * @gen_lock: Whether in gen-lock mode
23 * @delay: Delay counter
24 * @reset: Reset Channel
36 int delay; member
37 int reset; member
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| /kernel/linux/linux-5.10/drivers/scsi/qla4xxx/ |
| D | ql4_83xx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2003-2013 QLogic Corporation
17 return readl((void __iomem *)(ha->nx_pcibase + addr)); in qla4_83xx_rd_reg()
22 writel(val, (void __iomem *)(ha->nx_pcibase + addr)); in qla4_83xx_wr_reg()
30 qla4_83xx_wr_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num), addr); in qla4_83xx_set_win_base()
31 val = qla4_83xx_rd_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num)); in qla4_83xx_set_win_base()
91 __func__, ha->func_num, lock_owner); in qla4_83xx_flash_lock()
98 qla4_83xx_wr_reg(ha, QLA83XX_FLASH_LOCK_ID, ha->func_num); in qla4_83xx_flash_lock()
169 flash_offset = addr & (QLA83XX_FLASH_SECTOR_SIZE - 1); in qla4_83xx_lockless_flash_read_u32()
188 (QLA83XX_FLASH_SECTOR_SIZE - 1)) { in qla4_83xx_lockless_flash_read_u32()
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| /kernel/linux/linux-4.19/drivers/scsi/qla4xxx/ |
| D | ql4_83xx.c | 3 * Copyright (c) 2003-2013 QLogic Corporation
18 return readl((void __iomem *)(ha->nx_pcibase + addr)); in qla4_83xx_rd_reg()
23 writel(val, (void __iomem *)(ha->nx_pcibase + addr)); in qla4_83xx_wr_reg()
31 qla4_83xx_wr_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num), addr); in qla4_83xx_set_win_base()
32 val = qla4_83xx_rd_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num)); in qla4_83xx_set_win_base()
92 __func__, ha->func_num, lock_owner); in qla4_83xx_flash_lock()
99 qla4_83xx_wr_reg(ha, QLA83XX_FLASH_LOCK_ID, ha->func_num); in qla4_83xx_flash_lock()
170 flash_offset = addr & (QLA83XX_FLASH_SECTOR_SIZE - 1); in qla4_83xx_lockless_flash_read_u32()
189 (QLA83XX_FLASH_SECTOR_SIZE - 1)) { in qla4_83xx_lockless_flash_read_u32()
207 if (flash_offset > (QLA83XX_FLASH_SECTOR_SIZE - 1)) { in qla4_83xx_lockless_flash_read_u32()
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| /kernel/linux/linux-4.19/include/linux/dma/ |
| D | xilinx_dma.h | 4 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
15 #include <linux/dma-mapping.h>
19 * struct xilinx_vdma_config - VDMA Configuration structure
20 * @frm_dly: Frame delay
21 * @gen_lock: Whether in gen-lock mode
27 * @delay: Delay counter
28 * @reset: Reset Channel
40 int delay; member
41 int reset; member
|