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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/mmc/
Dmmc-pwrseq-simple.txt4 common properties between various SOC designs. It thus enables us to use the
8 - compatible : contains "mmc-pwrseq-simple".
11 - reset-gpios : contains a list of GPIO specifiers. The reset GPIOs are asserted
13 They will be de-asserted right after the power has been provided to the
15 - clocks : Must contain an entry for the entry in clock-names.
16 See ../clocks/clock-bindings.txt for details.
17 - clock-names : Must include the following entry:
19 - post-power-on-delay-ms : Delay in ms after powering the card and
20 de-asserting the reset-gpios (if any)
21 - power-off-delay-us : Delay in us after asserting the reset-gpios (if any)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dmdio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
17 bus. These should follow the generic ethernet-phy.yaml document, or
24 "#address-cells":
27 "#size-cells":
30 reset-gpios:
[all …]
Dhisilicon-femac.txt4 - compatible: should contain one of the following version strings:
5 * "hisilicon,hisi-femac-v1"
6 * "hisilicon,hisi-femac-v2"
7 and the soc string "hisilicon,hi3516cv300-femac".
8 - reg: specifies base physical address(s) and size of the device registers.
11 - interrupts: should contain the MAC interrupt.
12 - clocks: A phandle to the MAC main clock.
13 - resets: should contain the phandle to the MAC reset signal(required) and
14 the PHY reset signal(optional).
15 - reset-names: should contain the reset signal name "mac"(required)
[all …]
Dhisilicon-hix5hd2-gmac.txt4 - compatible: should contain one of the following SoC strings:
5 * "hisilicon,hix5hd2-gmac"
6 * "hisilicon,hi3798cv200-gmac"
7 * "hisilicon,hi3516a-gmac"
9 * "hisilicon,hisi-gmac-v1"
10 * "hisilicon,hisi-gmac-v2"
13 - reg: specifies base physical address(s) and size of the device registers.
16 - interrupts: should contain the MAC interrupt.
17 - #address-cells: must be <1>.
18 - #size-cells: must be <0>.
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Dmmc-pwrseq-simple.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
14 of common properties between various SOC designs. It thus enables us to use
19 const: mmc-pwrseq-simple
21 reset-gpios:
26 contains a list of GPIO specifiers. The reset GPIOs are asserted
28 They will be de-asserted right after the power has been provided to the
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/
Dhisilicon-femac.txt4 - compatible: should contain one of the following version strings:
5 * "hisilicon,hisi-femac-v1"
6 * "hisilicon,hisi-femac-v2"
7 and the soc string "hisilicon,hi3516cv300-femac".
8 - reg: specifies base physical address(s) and size of the device registers.
11 - interrupts: should contain the MAC interrupt.
12 - clocks: A phandle to the MAC main clock.
13 - resets: should contain the phandle to the MAC reset signal(required) and
14 the PHY reset signal(optional).
15 - reset-names: should contain the reset signal name "mac"(required)
[all …]
Dhisilicon-hix5hd2-gmac.txt4 - compatible: should contain one of the following SoC strings:
5 * "hisilicon,hix5hd2-gmac"
6 * "hisilicon,hi3798cv200-gmac"
7 * "hisilicon,hi3516a-gmac"
9 * "hisilicon,hisi-gmac-v1"
10 * "hisilicon,hisi-gmac-v2"
13 - reg: specifies base physical address(s) and size of the device registers.
16 - interrupts: should contain the MAC interrupt.
17 - #address-cells: must be <1>.
18 - #size-cells: must be <0>.
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/emulex/benet/
Dbe_hw.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2005-2016 Broadcom.
7 * linux-drivers@emulex.com
16 * The software must write this register twice to post any command. First,
33 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
39 /* Soft Reset register masks */
42 /* MPU semphore POST stage values */
44 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
45 #define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
46 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/emulex/benet/
Dbe_hw.h2 * Copyright (C) 2005-2016 Broadcom.
11 * linux-drivers@emulex.com
20 * The software must write this register twice to post any command. First,
37 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
43 /* Soft Reset register masks */
46 /* MPU semphore POST stage values */
48 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
49 #define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
50 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
131 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx6qdl-apf6.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
9 reg_1p8v: regulator-1p8v {
10 compatible = "regulator-fixed";
11 regulator-name = "1P8V";
12 regulator-min-microvolt = <1800000>;
13 regulator-max-microvolt = <1800000>;
14 regulator-always-on;
15 vin-supply = <&reg_3p3v>;
[all …]
Dsun8i-s3-pinecube.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
6 /dts-v1/;
7 #include "sun8i-v3.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
13 compatible = "pine64,pinecube", "sochip,s3", "allwinner,sun8i-v3";
20 stdout-path = "serial0:115200n8";
24 compatible = "gpio-leds";
38 compatible = "regulator-fixed";
39 regulator-name = "vcc5v0";
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-h5-nanopi-neo-plus2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 /dts-v1/;
6 #include "sun50i-h5.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/pinctrl/sun4i-a10.h>
14 compatible = "friendlyarm,nanopi-neo-plus2", "allwinner,sun50i-h5";
22 stdout-path = "serial0:115200n8";
26 compatible = "gpio-leds";
31 default-state = "on";
[all …]
/kernel/linux/linux-5.10/drivers/w1/
Dw1_io.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/delay.h>
48 * w1_touch_bit() - Generates a write-0 or write-1 cycle and samples the level.
50 * @bit: 0 - write a 0, 1 - write a 0 read the level
54 if (dev->bus_master->touch_bit) in w1_touch_bit()
55 return dev->bus_master->touch_bit(dev->bus_master->data, bit); in w1_touch_bit()
66 * w1_write_bit() - Generates a write-0 or write-1 cycle.
70 * Only call if dev->bus_master->touch_bit is NULL
79 dev->bus_master->write_bit(dev->bus_master->data, 0); in w1_write_bit()
81 dev->bus_master->write_bit(dev->bus_master->data, 1); in w1_write_bit()
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/ingenic/
Dcu1830-neo.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/clock/ingenic,tcu.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "yna,cu1830-neo", "ingenic,x1830";
11 model = "YSH & ATIL General Board CU1830-Neo";
18 stdout-path = "serial1:115200n8";
27 compatible = "gpio-leds";
28 led-0 {
[all …]
Dcu1000-neo.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/clock/ingenic,tcu.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "yna,cu1000-neo", "ingenic,x1000e";
11 model = "YSH & ATIL General Board CU1000-Neo";
18 stdout-path = "serial2:115200n8";
27 compatible = "gpio-leds";
28 led-0 {
[all …]
/kernel/linux/linux-4.19/drivers/w1/
Dw1_io.c17 #include <linux/delay.h>
57 * w1_touch_bit() - Generates a write-0 or write-1 cycle and samples the level.
59 * @bit: 0 - write a 0, 1 - write a 0 read the level
63 if (dev->bus_master->touch_bit) in w1_touch_bit()
64 return dev->bus_master->touch_bit(dev->bus_master->data, bit); in w1_touch_bit()
75 * w1_write_bit() - Generates a write-0 or write-1 cycle.
79 * Only call if dev->bus_master->touch_bit is NULL
88 dev->bus_master->write_bit(dev->bus_master->data, 0); in w1_write_bit()
90 dev->bus_master->write_bit(dev->bus_master->data, 1); in w1_write_bit()
93 dev->bus_master->write_bit(dev->bus_master->data, 0); in w1_write_bit()
[all …]
/kernel/linux/linux-5.10/drivers/mmc/core/
Dpwrseq_simple.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <linux/delay.h>
39 struct gpio_descs *reset_gpios = pwrseq->reset_gpios; in mmc_pwrseq_simple_set_gpios_value()
43 int nvalues = reset_gpios->ndescs; in mmc_pwrseq_simple_set_gpios_value()
54 gpiod_set_array_value_cansleep(nvalues, reset_gpios->desc, in mmc_pwrseq_simple_set_gpios_value()
55 reset_gpios->info, values); in mmc_pwrseq_simple_set_gpios_value()
63 struct mmc_pwrseq_simple *pwrseq = to_pwrseq_simple(host->pwrseq); in mmc_pwrseq_simple_pre_power_on()
65 if (!IS_ERR(pwrseq->ext_clk) && !pwrseq->clk_enabled) { in mmc_pwrseq_simple_pre_power_on()
66 clk_prepare_enable(pwrseq->ext_clk); in mmc_pwrseq_simple_pre_power_on()
67 pwrseq->clk_enabled = true; in mmc_pwrseq_simple_pre_power_on()
[all …]
/kernel/linux/linux-4.19/drivers/mmc/core/
Dpwrseq_simple.c19 #include <linux/delay.h>
40 struct gpio_descs *reset_gpios = pwrseq->reset_gpios; in mmc_pwrseq_simple_set_gpios_value()
44 int nvalues = reset_gpios->ndescs; in mmc_pwrseq_simple_set_gpios_value()
53 gpiod_set_array_value_cansleep(nvalues, reset_gpios->desc, values); in mmc_pwrseq_simple_set_gpios_value()
60 struct mmc_pwrseq_simple *pwrseq = to_pwrseq_simple(host->pwrseq); in mmc_pwrseq_simple_pre_power_on()
62 if (!IS_ERR(pwrseq->ext_clk) && !pwrseq->clk_enabled) { in mmc_pwrseq_simple_pre_power_on()
63 clk_prepare_enable(pwrseq->ext_clk); in mmc_pwrseq_simple_pre_power_on()
64 pwrseq->clk_enabled = true; in mmc_pwrseq_simple_pre_power_on()
72 struct mmc_pwrseq_simple *pwrseq = to_pwrseq_simple(host->pwrseq); in mmc_pwrseq_simple_post_power_on()
76 if (pwrseq->post_power_on_delay_ms) in mmc_pwrseq_simple_post_power_on()
[all …]
/kernel/linux/linux-5.10/drivers/clk/tegra/
Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
[all …]
/kernel/linux/linux-4.19/drivers/clk/tegra/
Dclk.h20 #include <linux/clk-provider.h>
22 #include <linux/delay.h>
25 * struct tegra_clk_sync_source - external clock source from codec
27 * @hw: handle between common and hardware-specific interfaces
47 * struct tegra_clk_frac_div - fractional divider clock
49 * @hw: handle between common and hardware-specific interfaces
51 * @flags: hardware-specific flags
58 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
59 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
61 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Drk3288-veyron-minnie.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
9 #include "rk3288-veyron-chromebook.dtsi"
13 compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3",
14 "google,veyron-minnie-rev2", "google,veyron-minnie-rev1",
15 "google,veyron-minnie-rev0", "google,veyron-minnie",
18 backlight_regulator: backlight-regulator {
19 compatible = "regulator-fixed";
20 enable-active-high;
22 pinctrl-names = "default";
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Dsram242x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mach-omap2/sram242x.S
9 * Richard Woodruff <r-woodruff2@ti.com>
31 stmfd sp!, {r0 - r12, lr} @ save registers on stack
39 str r3, [r2] @ go to L1-freq operation
62 mov r9, #0x0 @ shift back to L0-voltage
67 str r3, [r2] @ go to L0-freq operation
69 /* reset entry mode for dllctrl */
82 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
[all …]
Dsram243x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mach-omap2/sram243x.S
9 * Richard Woodruff <r-woodruff2@ti.com>
31 stmfd sp!, {r0 - r12, lr} @ save registers on stack
39 str r3, [r2] @ go to L1-freq operation
62 mov r9, #0x0 @ shift back to L0-voltage
67 str r3, [r2] @ go to L0-freq operation
69 /* reset entry mode for dllctrl */
82 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-omap2/
Dsram243x.S2 * linux/arch/arm/mach-omap2/sram243x.S
8 * Richard Woodruff <r-woodruff2@ti.com>
23 * MA 02111-1307 USA
45 stmfd sp!, {r0 - r12, lr} @ save registers on stack
53 str r3, [r2] @ go to L1-freq operation
76 mov r9, #0x0 @ shift back to L0-voltage
81 str r3, [r2] @ go to L0-freq operation
83 /* reset entry mode for dllctrl */
96 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
100 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
[all …]
Dsram242x.S2 * linux/arch/arm/mach-omap2/sram242x.S
8 * Richard Woodruff <r-woodruff2@ti.com>
23 * MA 02111-1307 USA
45 stmfd sp!, {r0 - r12, lr} @ save registers on stack
53 str r3, [r2] @ go to L1-freq operation
76 mov r9, #0x0 @ shift back to L0-voltage
81 str r3, [r2] @ go to L0-freq operation
83 /* reset entry mode for dllctrl */
96 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
100 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
[all …]

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