| /kernel/liteos_m/targets/riscv_nuclei_gd32vf103_soc_gcc/SoC/gd32vf103/Common/Include/ |
| D | gd32vf103_rcu.h | 5 \version 2019-6-5, V1.0.0, firmware for GD32VF103
11 Redistribution and use in source and binary forms, with or without modification,
14 1. Redistributions of source code must retain the above copyright notice, this
48 #define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */
49 #define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */
54 #define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock registe…
55 #define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */
57 #define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage regi…
84 #define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */
88 #define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selectio…
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| /kernel/liteos_m/targets/riscv_nuclei_gd32vf103_soc_gcc/SoC/gd32vf103/Common/Source/Drivers/ |
| D | gd32vf103_rcu.c | 5 \version 2019-6-5, V1.0.0, firmware for GD32VF103
11 Redistribution and use in source and binary forms, with or without modification,
14 1. Redistributions of source code must retain the above copyright notice, this
50 /* reset CFG0 register */ in rcu_deinit()
54 /* reset CTL register */ in rcu_deinit()
58 /* reset INT and CFG1 register */ in rcu_deinit()
153 \brief reset the peripherals
154 \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum
156 \arg RCU_GPIOxRST (x=A,B,C,D,E): reset GPIO ports
157 \arg RCU_AFRST : reset alternate function clock
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| D | gd32vf103_gpio.c | 5 \version 2019-6-5, V1.0.0, firmware for GD32VF103
11 Redistribution and use in source and binary forms, with or without modification,
14 1. Redistributions of source code must retain the above copyright notice, this
37 #define AFIO_EXTI_SOURCE_MASK ((uint8_t)0x03U) /*!< AFIO exti source selection…
38 #define AFIO_EXTI_SOURCE_FIELDS ((uint8_t)0x04U) /*!< select AFIO exti source re…
39 #define LSB_16BIT_MASK ((uint16_t)0xFFFFU) /*!< LSB 16-bit mask */
48 \brief reset GPIO port
57 /* reset GPIOA */ in gpio_deinit()
62 /* reset GPIOB */ in gpio_deinit()
67 /* reset GPIOC */ in gpio_deinit()
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| /kernel/linux/linux-4.19/drivers/reset/ |
| D | Kconfig | 5 bool "Reset Controller Support"
8 Generic Reset Controller support.
10 This framework is designed to abstract reset handling of devices
11 via GPIOs or SoC-internal reset controller modules.
18 tristate "Altera Arria10 System Resource Reset"
21 This option enables support for the external reset functions for
25 bool "AR71xx Reset Driver" if COMPILE_TEST
28 This enables the ATH79 reset controller driver that supports the
29 AR71xx SoC reset controller.
32 bool "AXS10x Reset Driver" if COMPILE_TEST
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| /kernel/linux/linux-5.10/drivers/video/fbdev/via/ |
| D | via_clock.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
12 #include <linux/via-core.h>
30 return ((pll.divisor - 2) << 16) in k800_encode_pll()
32 | (pll.multiplier - 2); in k800_encode_pll()
44 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in cle266_set_primary_pll_encoded()
47 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in cle266_set_primary_pll_encoded()
52 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in k800_set_primary_pll_encoded()
56 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in k800_set_primary_pll_encoded()
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| /kernel/linux/linux-4.19/arch/arm/mach-omap1/ |
| D | reset.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * OMAP1 reset support
14 /* ARM_SYSST bit shifts related to SoC reset sources */
20 /* Standardized reset source bits (across all OMAP SoCs) */
31 * "Global Software Reset Affects Traffic Controller Frequency". in omap1_restart()
42 * omap1_get_reset_sources - return the source of the SoC's last reset
44 * Returns bits that represent the last reset source for the SoC. The
|
| /kernel/linux/linux-5.10/arch/arm/mach-omap1/ |
| D | reset.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * OMAP1 reset support
14 /* ARM_SYSST bit shifts related to SoC reset sources */
20 /* Standardized reset source bits (across all OMAP SoCs) */
31 * "Global Software Reset Affects Traffic Controller Frequency". in omap1_restart()
42 * omap1_get_reset_sources - return the source of the SoC's last reset
44 * Returns bits that represent the last reset source for the SoC. The
|
| /kernel/linux/linux-4.19/drivers/video/fbdev/via/ |
| D | via_clock.c | 2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 #include <linux/via-core.h>
45 return ((pll.divisor - 2) << 16) in k800_encode_pll()
47 | (pll.multiplier - 2); in k800_encode_pll()
59 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in cle266_set_primary_pll_encoded()
62 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in cle266_set_primary_pll_encoded()
67 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in k800_set_primary_pll_encoded()
71 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in k800_set_primary_pll_encoded()
[all …]
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| /kernel/linux/linux-5.10/drivers/reset/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
22 This option enables support for the external reset functions for
26 bool "AR71xx Reset Driver" if COMPILE_TEST
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
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|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | qcom,gcc-msm8996.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8996.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for MSM8996
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
18 - dt-bindings/clock/qcom,gcc-msm8996.h
22 const: qcom,gcc-msm8996
26 - description: XO source
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| D | qcom,gcc-sc7180.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sc7180.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for SC7180
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
18 - dt-bindings/clock/qcom,gcc-sc7180.h
22 const: qcom,gcc-sc7180
26 - description: Board XO source
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| D | qcom,gpucc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller Binding
10 - Taniya Das <tdas@codeaurora.org>
17 dt-bindings/clock/qcom,gpucc-sdm845.h
18 dt-bindings/clock/qcom,gpucc-sc7180.h
19 dt-bindings/clock/qcom,gpucc-sm8150.h
20 dt-bindings/clock/qcom,gpucc-sm8250.h
25 - qcom,sdm845-gpucc
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| D | qcom,sdm845-dispcc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller Binding for SDM845
10 - Taniya Das <tdas@codeaurora.org>
16 See also dt-bindings/clock/qcom,dispcc-sdm845.h.
20 const: qcom,sdm845-dispcc
27 - description: Board XO source
28 - description: GPLL0 source from GCC
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| D | qcom,msm8998-gpucc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,msm8998-gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller Binding for MSM8998
10 - Taniya Das <tdas@codeaurora.org>
16 See also dt-bindings/clock/qcom,gpucc-msm8998.h.
20 const: qcom,msm8998-gpucc
24 - description: Board XO source
25 - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src)
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/input/ |
| D | nvidia,tegra20-kbc.txt | 7 - compatible: "nvidia,tegra20-kbc"
8 - reg: Register base address of KBC.
9 - interrupts: Interrupt number for the KBC.
10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
14 - linux,keymap: The keymap for keys as described in the binding document
15 devicetree/bindings/input/matrix-keymap.txt.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/input/ |
| D | nvidia,tegra20-kbc.txt | 7 - compatible: "nvidia,tegra20-kbc"
8 - reg: Register base address of KBC.
9 - interrupts: Interrupt number for the KBC.
10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
14 - linux,keymap: The keymap for keys as described in the binding document
15 devicetree/bindings/input/matrix-keymap.txt.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/power/reset/ |
| D | gpio-restart.txt | 4 This binding supports level and edge triggered reset. At driver load
6 handler. If the optional properties 'open-source' is not found, the GPIO line
12 triggering a level triggered reset condition. This will also cause an
13 inactive->active edge condition, triggering positive edge triggered
14 reset. After a delay specified by active-delay, the GPIO is set to
15 inactive, thus causing an active->inactive edge, triggering negative edge
16 triggered reset. After a delay specified by inactive-delay, the GPIO
17 is driven active again. After a delay specified by wait-delay, the
21 - compatible : should be "gpio-restart".
22 - gpios : The GPIO to set high/low, see "gpios property" in
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|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/reset/ |
| D | gpio-restart.txt | 4 This binding supports level and edge triggered reset. At driver load
6 handler. If the optional properties 'open-source' is not found, the GPIO line
12 triggering a level triggered reset condition. This will also cause an
13 inactive->active edge condition, triggering positive edge triggered
14 reset. After a delay specified by active-delay, the GPIO is set to
15 inactive, thus causing an active->inactive edge, triggering negative edge
16 triggered reset. After a delay specified by inactive-delay, the GPIO
17 is driven active again. After a delay specified by wait-delay, the
21 - compatible : should be "gpio-restart".
22 - gpios : The GPIO to set high/low, see "gpios property" in
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| /kernel/linux/linux-4.19/arch/sparc/include/asm/ |
| D | bbc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
24 #define BBC_PSRC 0x08 /* [W] POR Source */
25 #define BBC_XSRC 0x0c /* [B] XIR Source */
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
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| /kernel/linux/linux-5.10/arch/sparc/include/asm/ |
| D | bbc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
24 #define BBC_PSRC 0x08 /* [W] POR Source */
25 #define BBC_XSRC 0x0c /* [B] XIR Source */
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
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| /kernel/linux/linux-4.19/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_irq.c | 33 * passed to amdgpu IRQ handler which is responsible for detecting source and
64 * amdgpu_hotplug_work_func - work handler for display hotplug event
83 struct drm_device *dev = adev->ddev; in amdgpu_hotplug_work_func()
84 struct drm_mode_config *mode_config = &dev->mode_config; in amdgpu_hotplug_work_func()
87 mutex_lock(&mode_config->mutex); in amdgpu_hotplug_work_func()
88 list_for_each_entry(connector, &mode_config->connector_list, head) in amdgpu_hotplug_work_func()
90 mutex_unlock(&mode_config->mutex); in amdgpu_hotplug_work_func()
96 * amdgpu_irq_reset_work_func - execute GPU reset
100 * Execute scheduled GPU reset (Cayman+).
101 * This function is called when the IRQ handler thinks we need a GPU reset.
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| /kernel/linux/linux-5.10/drivers/net/ethernet/mellanox/mlx4/ |
| D | reset.c | 8 * COPYING in the main directory of this source tree, or the
11 * Redistribution and use in source and binary forms, with or
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
44 void __iomem *reset; in mlx4_reset() local
65 * Reset the chip. This is somewhat ugly because we have to in mlx4_reset()
66 * save off the PCI header before reset and then restore it in mlx4_reset()
74 err = -ENOMEM; in mlx4_reset()
79 pcie_cap = pci_pcie_cap(dev->persist->pdev); in mlx4_reset()
84 if (pci_read_config_dword(dev->persist->pdev, i * 4, in mlx4_reset()
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| /kernel/linux/linux-4.19/drivers/net/ethernet/mellanox/mlx4/ |
| D | reset.c | 8 * COPYING in the main directory of this source tree, or the
11 * Redistribution and use in source and binary forms, with or
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
44 void __iomem *reset; in mlx4_reset() local
65 * Reset the chip. This is somewhat ugly because we have to in mlx4_reset()
66 * save off the PCI header before reset and then restore it in mlx4_reset()
74 err = -ENOMEM; in mlx4_reset()
79 pcie_cap = pci_pcie_cap(dev->persist->pdev); in mlx4_reset()
84 if (pci_read_config_dword(dev->persist->pdev, i * 4, in mlx4_reset()
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/ |
| D | open-pic.txt | 13 - compatible: Specifies the compatibility list for the PIC. The type
14 shall be <string> and the value shall include "open-pic".
16 - reg: Specifies the base physical address(s) and size(s) of this
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
19 - interrupt-controller: The presence of this property identifies the node
22 - #interrupt-cells: Specifies the number of cells needed to encode an
23 interrupt source. The type shall be a <u32> and the value shall be 2.
25 - #address-cells: Specifies the number of cells needed to encode an
27 'interrupt-map' nodes do not have to specify a parent unit address.
31 - pic-no-reset: The presence of this property indicates that the PIC
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | open-pic.txt | 13 - compatible: Specifies the compatibility list for the PIC. The type
14 shall be <string> and the value shall include "open-pic".
16 - reg: Specifies the base physical address(s) and size(s) of this
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
19 - interrupt-controller: The presence of this property identifies the node
22 - #interrupt-cells: Specifies the number of cells needed to encode an
23 interrupt source. The type shall be a <u32> and the value shall be 2.
25 - #address-cells: Specifies the number of cells needed to encode an
27 'interrupt-map' nodes do not have to specify a parent unit address.
31 - pic-no-reset: The presence of this property indicates that the PIC
[all …]
|