Searched full:reset (Results 1 – 25 of 7624) sorted by relevance
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/reset/ |
| D | zynq-reset.txt | 1 Xilinx Zynq Reset Manager
8 - compatible: "xlnx,zynq-reset"
12 - #reset-cells: Must be 1
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
18 compatible = "xlnx,zynq-reset";
20 #reset-cells = <1>;
24 Reset outputs:
25 0 : soft reset
26 32 : ddr reset
27 64 : topsw reset
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| D | socionext,uniphier-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-reset.yaml#
7 title: UniPhier reset controller
15 - description: System reset
17 - socionext,uniphier-ld4-reset
18 - socionext,uniphier-pro4-reset
19 - socionext,uniphier-sld8-reset
20 - socionext,uniphier-pro5-reset
21 - socionext,uniphier-pxs2-reset
22 - socionext,uniphier-ld6b-reset
23 - socionext,uniphier-ld11-reset
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| D | reset.txt | 1 = Reset Signal Device Tree Bindings =
3 This binding is intended to represent the hardware reset signals present
4 internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
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| D | ti-syscon-reset.txt | 1 TI SysCon Reset Controller
4 Almost all SoCs have hardware modules that require reset control in addition
5 to clock and power control for their functionality. The reset control is
12 A SysCon Reset Controller node defines a device that uses a syscon node
13 and provides reset management functionality for various hardware modules
16 SysCon Reset Controller Node
18 Each of the reset provider/controller nodes should be a child of a syscon
27 "ti,syscon-reset"
28 - #reset-cells : Should be 1. Please see the reset consumer node below
30 - ti,reset-bits : Contains the reset control register information
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/reset/ |
| D | zynq-reset.txt | 1 Xilinx Zynq Reset Manager
8 - compatible: "xlnx,zynq-reset"
12 - #reset-cells: Must be 1
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
18 compatible = "xlnx,zynq-reset";
20 #reset-cells = <1>;
24 Reset outputs:
25 0 : soft reset
26 32 : ddr reset
27 64 : topsw reset
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| D | uniphier-reset.txt | 1 UniPhier reset controller
4 System reset
9 "socionext,uniphier-ld4-reset" - for LD4 SoC
10 "socionext,uniphier-pro4-reset" - for Pro4 SoC
11 "socionext,uniphier-sld8-reset" - for sLD8 SoC
12 "socionext,uniphier-pro5-reset" - for Pro5 SoC
13 "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC
14 "socionext,uniphier-ld11-reset" - for LD11 SoC
15 "socionext,uniphier-ld20-reset" - for LD20 SoC
16 "socionext,uniphier-pxs3-reset" - for PXs3 SoC
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| D | reset.txt | 1 = Reset Signal Device Tree Bindings =
3 This binding is intended to represent the hardware reset signals present
4 internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
[all …]
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| D | ti-syscon-reset.txt | 1 TI SysCon Reset Controller
4 Almost all SoCs have hardware modules that require reset control in addition
5 to clock and power control for their functionality. The reset control is
12 A SysCon Reset Controller node defines a device that uses a syscon node
13 and provides reset management functionality for various hardware modules
16 SysCon Reset Controller Node
18 Each of the reset provider/controller nodes should be a child of a syscon
27 "ti,syscon-reset"
28 - #reset-cells : Should be 1. Please see the reset consumer node below
30 - ti,reset-bits : Contains the reset control register information
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| /kernel/linux/linux-5.10/drivers/reset/ |
| D | Kconfig | 6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
22 This option enables support for the external reset functions for
26 bool "AR71xx Reset Driver" if COMPILE_TEST
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
33 bool "AXS10x Reset Driver" if COMPILE_TEST
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| D | Makefile | 6 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
7 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
8 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
9 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
10 obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
11 obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
12 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
13 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
14 obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
15 obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
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| D | reset-ti-sci.c | 2 * Texas Instrument's System Control Interface (TI-SCI) reset driver
22 #include <linux/reset-controller.h>
26 * struct ti_sci_reset_control - reset control structure
28 * @reset_mask: reset mask to use for toggling reset
38 * struct ti_sci_reset_data - reset controller information structure
39 * @rcdev: reset controller entity
40 * @dev: reset controller device pointer
42 * @idr: idr structure for mapping ids to reset control structures
55 * ti_sci_reset_set() - program a device's reset
56 * @rcdev: reset controller entity
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| D | reset-ti-syscon.c | 2 * TI SYSCON regmap reset driver
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/reset/ti-syscon.h>
28 * struct ti_syscon_reset_control - reset control structure
29 * @assert_offset: reset assert control register offset from syscon base
30 * @assert_bit: reset assert bit in the reset assert control register
31 * @deassert_offset: reset deassert control register offset from syscon base
32 * @deassert_bit: reset deassert bit in the reset deassert control register
33 * @status_offset: reset status register offset from syscon base
34 * @status_bit: reset status bit in the reset status register
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| D | core.c | 3 * Reset Controller framework
15 #include <linux/reset.h>
16 #include <linux/reset-controller.h>
26 * struct reset_control - a reset control
27 * @rcdev: a pointer to the reset controller device
28 * this reset control belongs to
29 * @list: list entry for the rcdev's reset controller list
30 * @id: ID of the reset controller in the reset
35 * @array: Is this an array of reset controls (1)?
36 * @deassert_count: Number of times this reset line has been deasserted
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| /kernel/linux/linux-4.19/drivers/reset/ |
| D | Kconfig | 5 bool "Reset Controller Support"
8 Generic Reset Controller support.
10 This framework is designed to abstract reset handling of devices
11 via GPIOs or SoC-internal reset controller modules.
18 tristate "Altera Arria10 System Resource Reset"
21 This option enables support for the external reset functions for
25 bool "AR71xx Reset Driver" if COMPILE_TEST
28 This enables the ATH79 reset controller driver that supports the
29 AR71xx SoC reset controller.
32 bool "AXS10x Reset Driver" if COMPILE_TEST
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| D | reset-ti-sci.c | 2 * Texas Instrument's System Control Interface (TI-SCI) reset driver
22 #include <linux/reset-controller.h>
26 * struct ti_sci_reset_control - reset control structure
28 * @reset_mask: reset mask to use for toggling reset
38 * struct ti_sci_reset_data - reset controller information structure
39 * @rcdev: reset controller entity
40 * @dev: reset controller device pointer
42 * @idr: idr structure for mapping ids to reset control structures
55 * ti_sci_reset_set() - program a device's reset
56 * @rcdev: reset controller entity
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| D | reset-ti-syscon.c | 2 * TI SYSCON regmap reset driver
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/reset/ti-syscon.h>
28 * struct ti_syscon_reset_control - reset control structure
29 * @assert_offset: reset assert control register offset from syscon base
30 * @assert_bit: reset assert bit in the reset assert control register
31 * @deassert_offset: reset deassert control register offset from syscon base
32 * @deassert_bit: reset deassert bit in the reset deassert control register
33 * @status_offset: reset status register offset from syscon base
34 * @status_bit: reset status bit in the reset status register
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| D | Makefile | 6 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
7 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
8 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
9 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
10 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
11 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
12 obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
13 obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
14 obj-$(CONFIG_RESET_MESON) += reset-meson.o
15 obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
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| D | core.c | 2 * Reset Controller framework
19 #include <linux/reset.h>
20 #include <linux/reset-controller.h>
30 * struct reset_control - a reset control
31 * @rcdev: a pointer to the reset controller device
32 * this reset control belongs to
33 * @list: list entry for the rcdev's reset controller list
34 * @id: ID of the reset controller in the reset
38 * @deassert_cnt: Number of times this reset line has been deasserted
39 * @triggered_count: Number of times this reset line has been reset. Currently
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| /kernel/linux/linux-5.10/drivers/net/ethernet/intel/i40e/ |
| D | i40e_register.h | 9 #define I40E_PF_ARQBAH 0x00080180 /* Reset: EMPR */
10 #define I40E_PF_ARQBAL 0x00080080 /* Reset: EMPR */
11 #define I40E_PF_ARQH 0x00080380 /* Reset: EMPR */
14 #define I40E_PF_ARQLEN 0x00080280 /* Reset: EMPR */
23 #define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */
24 #define I40E_PF_ATQBAH 0x00080100 /* Reset: EMPR */
25 #define I40E_PF_ATQBAL 0x00080000 /* Reset: EMPR */
26 #define I40E_PF_ATQH 0x00080300 /* Reset: EMPR */
27 #define I40E_PF_ATQLEN 0x00080200 /* Reset: EMPR */
36 #define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */
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| /kernel/linux/linux-5.10/drivers/power/reset/ |
| D | at91-reset.c | 2 * Atmel AT91 SAM9 & SAMA5 SoCs reset code
24 #define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */
25 #define AT91_RSTC_PROCRST BIT(0) /* Processor Reset */
26 #define AT91_RSTC_PERRST BIT(2) /* Peripheral Reset */
27 #define AT91_RSTC_EXTRST BIT(3) /* External Reset */
30 #define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */
31 #define AT91_RSTC_URSTS BIT(0) /* User Reset Status */
32 #define AT91_RSTC_RSTTYP GENMASK(10, 8) /* Reset Type */
34 #define AT91_RSTC_SRCMP BIT(17) /* Software Reset Command in Progress */
36 #define AT91_RSTC_MR 0x08 /* Reset Controller Mode Register */
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/reset/ |
| D | keystone-reset.txt | 1 * Device tree bindings for Texas Instruments keystone reset
3 This node is intended to allow SoC reset in case of software reset
6 The Keystone SoCs can contain up to 4 watchdog timers to reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
8 block. The Reset Mux block can be configured to cause reset or not.
10 Additionally soft or hard reset can be configured.
14 - compatible: ti,keystone-reset
18 reset control registers.
26 - ti,soft-reset: Boolean option indicating soft reset.
27 By default hard reset is used.
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/power/reset/ |
| D | keystone-reset.txt | 1 * Device tree bindings for Texas Instruments keystone reset
3 This node is intended to allow SoC reset in case of software reset
6 The Keystone SoCs can contain up to 4 watchdog timers to reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
8 block. The Reset Mux block can be configured to cause reset or not.
10 Additionally soft or hard reset can be configured.
14 - compatible: ti,keystone-reset
18 reset control registers.
26 - ti,soft-reset: Boolean option indicating soft reset.
27 By default hard reset is used.
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| /kernel/linux/linux-4.19/drivers/infiniband/hw/i40iw/ |
| D | i40iw_register.h | 38 #define I40E_GLGEN_STAT 0x000B612C /* Reset: POR */
40 #define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */
54 #define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
62 …FINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */
63 #define I40E_GLHMC_VFPDINV(_i) (0x000C8300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CO…
67 #define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */
70 #define I40E_GLPCI_DREVID 0x0009C480 /* Reset: PCIR */
74 #define I40E_PFPE_AEQALLOC 0x00131180 /* Reset: PFR */
77 #define I40E_PFPE_CCQPHIGH 0x00008200 /* Reset: PFR */
80 #define I40E_PFPE_CCQPLOW 0x00008180 /* Reset: PFR */
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| /kernel/linux/linux-5.10/drivers/infiniband/hw/i40iw/ |
| D | i40iw_register.h | 38 #define I40E_GLGEN_STAT 0x000B612C /* Reset: POR */
40 #define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */
54 #define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
62 …FINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */
63 #define I40E_GLHMC_VFPDINV(_i) (0x000C8300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CO…
67 #define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */
70 #define I40E_GLPCI_DREVID 0x0009C480 /* Reset: PCIR */
74 #define I40E_PFPE_AEQALLOC 0x00131180 /* Reset: PFR */
77 #define I40E_PFPE_CCQPHIGH 0x00008200 /* Reset: PFR */
80 #define I40E_PFPE_CCQPLOW 0x00008180 /* Reset: PFR */
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| /kernel/linux/linux-5.10/include/linux/ |
| D | reset.h | 138 * to a reset controller.
139 * @dev: device to be reset by the controller
140 * @id: reset line name
147 * reset-controls.
159 * exclusive reference to a reset
161 * @dev: device to be reset by the controller
162 * @id: reset line name
165 * reset-controls returned by this function must be acquired via
180 * reset controller.
181 * @dev: device to be reset by the controller
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