| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/ata/ |
| D | sata-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/sata-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Serial AT attachment (SATA) controllers
10 - Linus Walleij <linus.walleij@linaro.org>
14 AT attachment (SATA) storage devices. It doesn't constitute a device tree
18 The SATA controller-specific device tree bindings are responsible for
23 pattern: "^sata(@.*)?$"
25 Specifies the host controller node. SATA host controller nodes are named
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| D | ahci-platform.txt | 1 * AHCI SATA Controller
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
4 Each SATA controller should have its own node.
6 It is possible, but not required, to represent each port as a sub-node.
7 It allows to enable each port independently when dealing with multiple
11 - compatible : compatible string, one of:
12 - "brcm,iproc-ahci"
13 - "hisilicon,hisi-ahci"
14 - "cavium,octeon-7130-ahci"
15 - "ibm,476gtr-ahci"
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| /kernel/linux/linux-4.19/arch/arm64/boot/dts/broadcom/stingray/ |
| D | stingray-sata.dtsi | 4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
33 sata {
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
40 compatible = "brcm,iproc-ahci", "generic-ahci";
42 reg-names = "ahci";
44 #address-cells = <1>;
45 #size-cells = <0>;
48 sata0_port0: sata-port@0 {
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/broadcom/stingray/ |
| D | stingray-sata.dtsi | 4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
33 sata {
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
40 compatible = "brcm,iproc-ahci", "generic-ahci";
42 reg-names = "ahci";
44 #address-cells = <1>;
45 #size-cells = <0>;
48 sata0_port0: sata-port@0 {
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/ata/ |
| D | ahci-platform.txt | 1 * AHCI SATA Controller
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
4 Each SATA controller should have its own node.
6 It is possible, but not required, to represent each port as a sub-node.
7 It allows to enable each port independently when dealing with multiple
11 - compatible : compatible string, one of:
12 - "allwinner,sun4i-a10-ahci"
13 - "brcm,iproc-ahci"
14 - "hisilicon,hisi-ahci"
15 - "cavium,octeon-7130-ahci"
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| D | sata_highbank.txt | 1 * Calxeda AHCI SATA Controller
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
4 The Calxeda SATA controller mostly conforms to the AHCI interface
6 Each SATA controller should have its own node.
9 - compatible : compatible list, contains "calxeda,hb-ahci"
10 - interrupts : <interrupt mapping for SATA IRQ>
11 - reg : <registers mapping>
14 - dma-coherent : Present if dma operations are coherent
15 - calxeda,port-phys : phandle-combophy and lane assignment, which maps each
16 SATA port to a combophy and a lane within that
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/phy/ |
| D | phy-miphy365x.txt | 5 for SATA and PCIe.
8 - compatible : Should be "st,miphy365x-phy"
9 - st,syscfg : Phandle / integer array property. Phandle of sysconfig group
11 an entry for each port sub-node, specifying the control
14 Required nodes : A sub-node is required for each channel the controller
16 'reg' and 'reg-names' properties are used inside these
20 Required properties (port (child) node):
21 - #phy-cells : Should be 1 (See second example)
22 Cell after port phandle is device type from:
23 - PHY_TYPE_SATA
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| D | nvidia,tegra124-xusb-padctl.txt | 11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
27 "port" is typically used to denote the physical USB receptacle. The device
28 tree binding in this document uses the term "port" to refer to the logical
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| D | phy-miphy28lp.txt | 5 for SATA, PCIe or USB3.
8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
10 which contain the SATA, PCIe or USB3 mode setting bits.
12 Required nodes : A sub-node is required for each channel the controller
14 'reg' and 'reg-names' properties are used inside these
18 Required properties (port (child) node):
19 - #phy-cells : Should be 1 (See second example)
20 Cell after port phandle is device type from:
21 - PHY_TYPE_SATA
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| D | brcm-sata-phy.txt | 4 - compatible: should be one or more of
5 "brcm,bcm7425-sata-phy"
6 "brcm,bcm7445-sata-phy"
7 "brcm,iproc-ns2-sata-phy"
8 "brcm,iproc-nsp-sata-phy"
9 "brcm,phy-sata3"
10 "brcm,iproc-sr-sata-phy"
11 - address-cells: should be 1
12 - size-cells: should be 0
13 - reg: register ranges for the PHY PCB interface
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | phy-miphy365x.txt | 5 for SATA and PCIe.
8 - compatible : Should be "st,miphy365x-phy"
9 - st,syscfg : Phandle / integer array property. Phandle of sysconfig group
11 an entry for each port sub-node, specifying the control
14 Required nodes : A sub-node is required for each channel the controller
16 'reg' and 'reg-names' properties are used inside these
20 Required properties (port (child) node):
21 - #phy-cells : Should be 1 (See second example)
22 Cell after port phandle is device type from:
23 - PHY_TYPE_SATA
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| D | nvidia,tegra124-xusb-padctl.txt | 11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
27 "port" is typically used to denote the physical USB receptacle. The device
28 tree binding in this document uses the term "port" to refer to the logical
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| D | phy-miphy28lp.txt | 5 for SATA, PCIe or USB3.
8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
10 which contain the SATA, PCIe or USB3 mode setting bits.
12 Required nodes : A sub-node is required for each channel the controller
14 'reg' and 'reg-names' properties are used inside these
18 Required properties (port (child) node):
19 - #phy-cells : Should be 1 (See second example)
20 Cell after port phandle is device type from:
21 - PHY_TYPE_SATA
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| D | brcm-sata-phy.txt | 4 - compatible: should be one or more of
5 "brcm,bcm7216-sata-phy"
6 "brcm,bcm7425-sata-phy"
7 "brcm,bcm7445-sata-phy"
8 "brcm,iproc-ns2-sata-phy"
9 "brcm,iproc-nsp-sata-phy"
10 "brcm,phy-sata3"
11 "brcm,iproc-sr-sata-phy"
12 "brcm,bcm63138-sata-phy"
13 - address-cells: should be 1
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| /kernel/linux/linux-5.10/drivers/scsi/mvsas/ |
| D | mv_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
28 /* driver compile-time configuration */
30 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
31 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
32 /* software requires power-of-2
40 MVS_ATA_CMD_SZ = 96, /* SATA command table buffer size */
43 MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
76 INT_SAS_SATA = (1U << 0), /* SAS/SATA event */
78 /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
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| /kernel/linux/linux-5.10/drivers/phy/tegra/ |
| D | xusb-tegra210.c | 1 // SPDX-License-Identifier: GPL-2.0-only
25 ((x) ? (11 + ((x) - 1) * 6) : 0)
259 /* must be called under padctl->lock */
262 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); in tegra210_pex_uphy_enable()
267 if (pcie->enable > 0) { in tegra210_pex_uphy_enable()
268 pcie->enable++; in tegra210_pex_uphy_enable()
272 err = clk_prepare_enable(pcie->pll); in tegra210_pex_uphy_enable()
276 err = reset_control_deassert(pcie->rst); in tegra210_pex_uphy_enable()
355 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
374 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
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| D | xusb-tegra124.c | 1 // SPDX-License-Identifier: GPL-2.0-only
229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
251 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable()
259 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_disable()
261 if (WARN_ON(padctl->enable == 0)) in tegra124_xusb_padctl_disable()
264 if (--padctl->enable > 0) in tegra124_xusb_padctl_disable()
284 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_disable()
291 struct tegra_xusb_usb3_port *port; in tegra124_usb3_save_context() local
295 port = tegra_xusb_find_usb3_port(padctl, index); in tegra124_usb3_save_context()
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| /kernel/linux/linux-4.19/drivers/scsi/mvsas/ |
| D | mv_defs.h | 6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
44 /* driver compile-time configuration */
46 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
47 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
48 /* software requires power-of-2
56 MVS_ATA_CMD_SZ = 96, /* SATA command table buffer size */
59 MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
92 INT_SAS_SATA = (1U << 0), /* SAS/SATA event */
94 /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
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| /kernel/linux/linux-4.19/drivers/phy/tegra/ |
| D | xusb-tegra210.c | 33 ((x) ? (11 + ((x) - 1) * 6) : 0)
251 /* must be called under padctl->lock */
254 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); in tegra210_pex_uphy_enable()
259 if (pcie->enable > 0) { in tegra210_pex_uphy_enable()
260 pcie->enable++; in tegra210_pex_uphy_enable()
264 err = clk_prepare_enable(pcie->pll); in tegra210_pex_uphy_enable()
268 err = reset_control_deassert(pcie->rst); in tegra210_pex_uphy_enable()
347 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
366 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
385 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
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| D | xusb-tegra124.c | 237 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
239 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
259 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable()
267 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_disable()
269 if (WARN_ON(padctl->enable == 0)) in tegra124_xusb_padctl_disable()
272 if (--padctl->enable > 0) in tegra124_xusb_padctl_disable()
292 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_disable()
299 struct tegra_xusb_usb3_port *port; in tegra124_usb3_save_context() local
303 port = tegra_xusb_find_usb3_port(padctl, index); in tegra124_usb3_save_context()
304 if (!port) in tegra124_usb3_save_context()
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| /kernel/linux/linux-4.19/drivers/phy/samsung/ |
| D | Kconfig | 5 tristate "EXYNOS SoC series Display Port PHY driver"
11 Support for Display Port PHY found on Samsung EXYNOS SoCs.
14 tristate "S5P/EXYNOS SoC series MIPI CSI-2/DSI PHY driver"
20 Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
67 are available - device and host.
83 tristate "Exynos5250 Sata SerDes/PHY driver"
92 Enable this to support SATA SerDes/Phy found on Samsung's
93 Exynos5250 based SoCs.This SerDes/Phy supports SATA 1.5 Gb/s,
94 SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds. It supports one SATA host
95 port to accept one SATA device.
|
| /kernel/linux/linux-5.10/drivers/scsi/aic94xx/ |
| D | aic94xx_dev.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Aic94xx SAS/SATA DDB management
16 #define FIND_FREE_DDB(_ha) find_first_zero_bit((_ha)->hw_prof.ddb_bitmap, \
17 (_ha)->hw_prof.max_ddbs)
18 #define SET_DDB(_ddb, _ha) set_bit(_ddb, (_ha)->hw_prof.ddb_bitmap)
19 #define CLEAR_DDB(_ddb, _ha) clear_bit(_ddb, (_ha)->hw_prof.ddb_bitmap)
26 if (ddb >= asd_ha->hw_prof.max_ddbs) { in asd_get_ddb()
27 ddb = -ENOMEM; in asd_get_ddb()
67 struct asd_ha_struct *asd_ha = dev->port->ha->lldd_ha; in asd_set_ddb_type()
68 int ddb = (int) (unsigned long) dev->lldd_dev; in asd_set_ddb_type()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | mvebu-gated-clock.txt | 12 -----------------------------------
20 15 sata0 SATA Host 0
25 30 sata1 SATA Host 0
29 -----------------------------------
37 14 sata0_link SATA 0 Link
38 15 sata0_core SATA 0 Core
43 20 sata1_link SATA 1 Link
44 21 sata1_core SATA 1 Core
49 28 crypto0_enc Cryptographic Unit Port 0 Encryption
50 29 crypto0_core Cryptographic Unit Port 0 Core
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/ |
| D | mvebu-gated-clock.txt | 12 -----------------------------------
20 15 sata0 SATA Host 0
25 30 sata1 SATA Host 0
29 -----------------------------------
37 14 sata0_link SATA 0 Link
38 15 sata0_core SATA 0 Core
43 20 sata1_link SATA 1 Link
44 21 sata1_core SATA 1 Core
49 28 crypto0_enc Cryptographic Unit Port 0 Encryption
50 29 crypto0_core Cryptographic Unit Port 0 Core
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| /kernel/linux/linux-5.10/drivers/phy/samsung/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 tristate "Exynos SoC series Display Port PHY driver"
12 Support for Display Port PHY found on Samsung Exynos SoCs.
15 tristate "S5P/Exynos SoC series MIPI CSI-2/DSI PHY driver"
21 Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
77 are available - device and host.
93 tristate "Exynos5250 Sata SerDes/PHY driver"
102 Enable this to support SATA SerDes/Phy found on Samsung's
103 Exynos5250 based SoCs.This SerDes/Phy supports SATA 1.5 Gb/s,
104 SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds. It supports one SATA host
[all …]
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