Searched full:sdclk (Results 1 – 25 of 56) sorted by relevance
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mmc/ |
| D | sdhci-cadence.txt | 56 - cdns,phy-dll-delay-sdclk:
57 Value of the delay introduced on the sdclk output
60 - cdns,phy-dll-delay-sdclk-hsmmc:
61 Value of the delay introduced on the sdclk output
79 cdns,phy-dll-delay-sdclk = <0>;
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| D | marvell,xenon-sdhci.txt | 131 clocks = <&sdclk>, <&axi_clk>;
167 clocks = <&sdclk>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | cdns,sdhci.yaml | 90 cdns,phy-dll-delay-sdclk:
92 Value of the delay introduced on the sdclk output for all modes except
98 cdns,phy-dll-delay-sdclk-hsmmc:
100 Value of the delay introduced on the sdclk output for HS200, HS400 and
133 cdns,phy-dll-delay-sdclk = <0>;
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| D | marvell,xenon-sdhci.txt | 131 clocks = <&sdclk>, <&axi_clk>;
167 clocks = <&sdclk>;
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| /kernel/linux/linux-4.19/drivers/mmc/host/ |
| D | sdhci-xenon-phy.c | 225 * 1. SDCLK frequency changes.
226 * 2. SDCLK is stopped and re-enabled.
463 * 2. SDCLK is higher than 52MHz in xenon_emmc_phy_strobe_delay_adj()
485 * If eMMC PHY Slow Mode is required in lower speed mode (SDCLK < 55MHz)
774 * PHY setting should be adjusted when SDCLK frequency, Bus Width
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| D | sdhci-cadence.c | 96 { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
97 { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
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| D | sdhci-xenon.c | 53 /* Set SDCLK-off-while-idle */
468 /* Disable SDCLK-Off-While-Idle before card init */ in xenon_sdhc_prepare()
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| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| D | sdhci-xenon-phy.c | 222 * 1. SDCLK frequency changes.
223 * 2. SDCLK is stopped and re-enabled.
460 * 2. SDCLK is higher than 52MHz in xenon_emmc_phy_strobe_delay_adj()
482 * If eMMC PHY Slow Mode is required in lower speed mode (SDCLK < 55MHz)
771 * PHY setting should be adjusted when SDCLK frequency, Bus Width
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| D | sdhci-cadence.c | 88 { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
89 { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
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| D | sdhci-xenon.c | 50 /* Set SDCLK-off-while-idle */
470 /* Disable SDCLK-Off-While-Idle before card init */ in xenon_sdhc_prepare()
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| D | sdhci-of-aspeed.c | 269 dev_err(&pdev->dev, "Unable to enable SDCLK\n"); in aspeed_sdc_probe()
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| D | uniphier-sd.c | 24 #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) // auto SDCLK stop
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| /kernel/linux/linux-5.10/drivers/cpufreq/ |
| D | sa1110-cpufreq.c | 152 * If SDCLK would invalidate the SDRAM timings, in sdram_calculate_timing()
153 * run SDCLK at half speed. in sdram_calculate_timing()
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| /kernel/linux/linux-4.19/drivers/cpufreq/ |
| D | sa1110-cpufreq.c | 155 * If SDCLK would invalidate the SDRAM timings, in sdram_calculate_timing()
156 * run SDCLK at half speed. in sdram_calculate_timing()
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| /kernel/linux/linux-4.19/drivers/video/fbdev/mbx/ |
| D | mbxdebugfs.c | 125 s += sprintf(s, "SDCLK = %08x\n", readl(SDCLK)); in clock_read_file()
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| D | regs.h | 36 #define SDCLK __REG_2700G(0x00000058) macro
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| /kernel/linux/linux-4.19/arch/arm64/boot/dts/socionext/ |
| D | uniphier-pxs3.dtsi | 340 cdns,phy-dll-delay-sdclk = <21>;
341 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
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| D | uniphier-ld11.dtsi | 420 cdns,phy-dll-delay-sdclk = <21>;
421 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
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| D | uniphier-ld20.dtsi | 527 cdns,phy-dll-delay-sdclk = <21>;
528 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/socionext/ |
| D | uniphier-ld11.dtsi | 455 cdns,phy-dll-delay-sdclk = <21>;
456 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
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| D | uniphier-pxs3.dtsi | 411 cdns,phy-dll-delay-sdclk = <21>;
412 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
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| D | uniphier-ld20.dtsi | 585 cdns,phy-dll-delay-sdclk = <21>;
586 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
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| /kernel/linux/linux-4.19/arch/arm/mach-pxa/ |
| D | mxm8x10.c | 178 GPIO22 - SDCLK
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| /kernel/linux/linux-5.10/arch/arm/mach-pxa/ |
| D | mxm8x10.c | 175 GPIO22 - SDCLK
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| /kernel/linux/linux-4.19/include/linux/mmc/ |
| D | host.h | 111 * switching might fail because the SDCLK is not really quiet.
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