| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/iommu/ |
| D | qcom,iommu.txt | 3 Qualcomm "B" family devices which are not compatible with arm-smmu have
4 a similar looking IOMMU but without access to the global register space,
6 to non-secure vs secure interrupt line.
10 - compatible : Should be one of:
12 "qcom,msm8916-iommu"
14 Followed by "qcom,msm-iommu-v1".
16 - clock-names : Should be a pair of "iface" (required for IOMMUs
17 register group access) and "bus" (required for
18 the IOMMUs underlying bus access).
20 - clocks : Phandles for respective clocks described by
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| D | msm,iommu-v0.txt | 5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
13 secure mode, in that order. For instances that don't support secure mode a
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
18 - clocks : List of clocks to be used during SMMU register access. See
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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| D | arm,smmu.txt | 12 - compatible : Should be one of:
14 "arm,smmu-v1"
15 "arm,smmu-v2"
16 "arm,mmu-400"
17 "arm,mmu-401"
18 "arm,mmu-500"
19 "cavium,smmu-v2"
24 - reg : Base address and size of the SMMU.
26 - #global-interrupts : The number of global interrupts exposed by the
29 - interrupts : Interrupt list, with the first #global-irqs entries
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| D | arm,smmu-v3.txt | 4 revisions, replacing the MMIO register interface with in-memory command
10 - compatible : Should include:
12 * "arm,smmu-v3" for any SMMUv3 compliant
16 - reg : Base address and size of the SMMU.
18 - interrupts : Non-secure interrupt list describing the wired
20 interrupt-names. If no wired interrupts are
23 - interrupt-names : When the interrupts property is present, should
25 * "eventq" - Event Queue not empty
26 * "priq" - PRI Queue not empty
27 * "cmdq-sync" - CMD_SYNC complete
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/iommu/ |
| D | qcom,iommu.txt | 3 Qualcomm "B" family devices which are not compatible with arm-smmu have
4 a similar looking IOMMU but without access to the global register space,
6 to non-secure vs secure interrupt line.
10 - compatible : Should be one of:
12 "qcom,msm8916-iommu"
14 Followed by "qcom,msm-iommu-v1".
16 - clock-names : Should be a pair of "iface" (required for IOMMUs
17 register group access) and "bus" (required for
18 the IOMMUs underlying bus access).
20 - clocks : Phandles for respective clocks described by
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| D | arm,smmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
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| D | msm,iommu-v0.txt | 5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
13 secure mode, in that order. For instances that don't support secure mode a
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
18 - clocks : List of clocks to be used during SMMU register access. See
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/nvmem/ |
| D | st,stm32-romem.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/st,stm32-romem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Factory-programmed data bindings
10 This represents STM32 Factory-programmed read only non-volatile area: locked
11 flash, OTP, read-only HW regs... This contains various information such as:
16 - Fabrice Gasnier <fabrice.gasnier@st.com>
19 - $ref: "nvmem.yaml#"
24 - st,stm32f4-otp
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/ |
| D | pmu.txt | 5 representation in the device tree should be done as under:-
9 - compatible : should be one of
10 "apm,potenza-pmu"
11 "arm,armv8-pmuv3"
12 "arm,cortex-a73-pmu"
13 "arm,cortex-a72-pmu"
14 "arm,cortex-a57-pmu"
15 "arm,cortex-a53-pmu"
16 "arm,cortex-a35-pmu"
17 "arm,cortex-a17-pmu"
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - arm,armv8-pmuv3 # Only for s/w models
24 - arm,arm1136-pmu
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | marvell,icu.txt | 2 --------------------------------
5 responsible for collecting all wired-interrupt sources in the CP and
8 These messages will access a different GIC memory area depending on
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
24 * "marvell,cp110-icu-sr"
25 * "marvell,cp110-icu-sei"
26 * "marvell,cp110-icu-rei"
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| /kernel/linux/linux-5.10/drivers/iommu/arm/arm-smmu/ |
| D | arm-smmu-impl.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 #define pr_fmt(fmt) "arm-smmu: " fmt
10 #include "arm-smmu.h"
44 /* Since we don't care for sGFAR, we can do without 64-bit accessors */
65 cs->id_base = atomic_fetch_add(smmu->num_context_banks, &context_count); in cavium_cfg_probe()
66 dev_notice(smmu->dev, "\tenabling workaround for Cavium erratum 27704\n"); in cavium_cfg_probe()
74 struct cavium_smmu *cs = container_of(smmu_domain->smmu, in cavium_init_context()
77 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S2) in cavium_init_context()
78 smmu_domain->cfg.vmid += cs->id_base; in cavium_init_context()
80 smmu_domain->cfg.asid += cs->id_base; in cavium_init_context()
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| /kernel/linux/linux-4.19/drivers/perf/ |
| D | arm_pmu_platform.c | 1 // SPDX-License-Identifier: GPL-2.0
30 int ret = -ENODEV; in probe_current_pmu()
34 for (; info->init != NULL; info++) { in probe_current_pmu()
35 if ((cpuid & info->mask) != info->cpuid) in probe_current_pmu()
37 ret = info->init(pmu); in probe_current_pmu()
48 struct pmu_hw_events __percpu *hw_events = pmu->hw_events; in pmu_parse_percpu_irq()
50 ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus); in pmu_parse_percpu_irq()
54 for_each_cpu(cpu, &pmu->supported_cpus) in pmu_parse_percpu_irq()
55 per_cpu(hw_events->irq, cpu) = irq; in pmu_parse_percpu_irq()
62 return !!of_find_property(node, "interrupt-affinity", NULL); in pmu_has_irq_affinity()
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| /kernel/linux/linux-5.10/drivers/perf/ |
| D | arm_pmu_platform.c | 1 // SPDX-License-Identifier: GPL-2.0
31 int ret = -ENODEV; in probe_current_pmu()
35 for (; info->init != NULL; info++) { in probe_current_pmu()
36 if ((cpuid & info->mask) != info->cpuid) in probe_current_pmu()
38 ret = info->init(pmu); in probe_current_pmu()
49 struct pmu_hw_events __percpu *hw_events = pmu->hw_events; in pmu_parse_percpu_irq()
51 ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus); in pmu_parse_percpu_irq()
55 for_each_cpu(cpu, &pmu->supported_cpus) in pmu_parse_percpu_irq()
56 per_cpu(hw_events->irq, cpu) = irq; in pmu_parse_percpu_irq()
63 return !!of_find_property(node, "interrupt-affinity", NULL); in pmu_has_irq_affinity()
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| /kernel/linux/linux-5.10/Documentation/driver-api/ |
| D | vfio.rst | 2 VFIO - "Virtual Function I/O" [1]_
7 allotted. This includes x86 hardware with AMD-Vi and Intel VT-d,
10 agnostic framework for exposing direct device access to userspace, in
11 a secure, IOMMU protected environment. In other words, this allows
12 safe [2]_, non-privileged, userspace drivers.
15 access ("device assignment") when configured for the highest possible
19 bare-metal device drivers [3]_.
22 field, also benefit from low-overhead, direct device access from
23 userspace. Examples include network adapters (often non-TCP/IP based)
28 and requires root privileges to access things like PCI configuration
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| /kernel/linux/linux-4.19/Documentation/ |
| D | vfio.txt | 2 VFIO - "Virtual Function I/O" [1]_
7 allotted. This includes x86 hardware with AMD-Vi and Intel VT-d,
10 agnostic framework for exposing direct device access to userspace, in
11 a secure, IOMMU protected environment. In other words, this allows
12 safe [2]_, non-privileged, userspace drivers.
15 access ("device assignment") when configured for the highest possible
19 bare-metal device drivers [3]_.
22 field, also benefit from low-overhead, direct device access from
23 userspace. Examples include network adapters (often non-TCP/IP based)
28 and requires root privileges to access things like PCI configuration
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| /kernel/linux/linux-5.10/drivers/rtc/ |
| D | rtc-mxc_v2.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
21 #define SRTC_LPCR_NSA BIT(11) /* lp non secure access */
26 #define SRTC_LPSR_NVES BIT(14) /* lp non-valid state exit status */
29 #define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */
30 #define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */
31 #define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */
32 #define SRTC_LPCR 0x10 /* LP Control Reg */
33 #define SRTC_LPSR 0x14 /* LP Status Reg */
34 #define SRTC_LPPDR 0x18 /* LP Power Supply Glitch Detector Reg */
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| /kernel/linux/linux-4.19/drivers/rtc/ |
| D | rtc-mxc_v2.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
20 #define SRTC_LPCR_NSA BIT(11) /* lp non secure access */
25 #define SRTC_LPSR_NVES BIT(14) /* lp non-valid state exit status */
28 #define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */
29 #define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */
30 #define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */
31 #define SRTC_LPCR 0x10 /* LP Control Reg */
32 #define SRTC_LPSR 0x14 /* LP Status Reg */
33 #define SRTC_LPPDR 0x18 /* LP Power Supply Glitch Detector Reg */
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| /kernel/linux/linux-5.10/arch/xtensa/include/asm/ |
| D | thread_info.h | 2 * include/asm-xtensa/thread_info.h
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
24 * low level task data that entry.S needs immediate access to
25 * - this struct should fit entirely inside of one cache line
26 * - this struct shares the supervisor stack pages
27 * - if the contents of this structure are changed, the assembly constants
51 unsigned long status; /* thread-synchronous flags */
73 * macros/functions for gaining access to the thread information structure
99 #define GET_THREAD_INFO(reg,sp) \ argument
100 extui reg, sp, 0, CURRENT_SHIFT; \
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| /kernel/linux/linux-5.10/drivers/iommu/ |
| D | ipmmu-vmsa.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU API for Renesas VMSA-compatible IPMMU
6 * Copyright (C) 2014-2020 Renesas Electronics Corporation
11 #include <linux/dma-iommu.h>
12 #include <linux/dma-mapping.h>
18 #include <linux/io-pgtable.h>
30 #include <asm/dma-iommu.h>
33 #define arm_iommu_attach_device(...) -ENODEV
39 #define IPMMU_CTX_INVALID -1
96 /* -----------------------------------------------------------------------------
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| /kernel/linux/linux-4.19/drivers/iommu/ |
| D | ipmmu-vmsa.c | 13 #include <linux/dma-iommu.h>
14 #include <linux/dma-mapping.h>
31 #include <asm/dma-iommu.h>
35 #define arm_iommu_attach_device(...) -ENODEV
40 #include "io-pgtable.h"
87 return dev->iommu_fwspec ? dev->iommu_fwspec->iommu_priv : NULL; in to_ipmmu()
92 /* -----------------------------------------------------------------------------
200 #define IMUCTR32(n) (0x0600 + (((n) - 32) * 16))
212 #define IMUASID32(n) (0x0608 + (((n) - 32) * 16))
218 /* -----------------------------------------------------------------------------
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interconnect/ |
| D | fsl,imx8m-noc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Leonard Crestez <leonard.crestez@nxp.com>
17 ("Global Programmers View") but not all. Access to this area might be denied
18 for normal (non-secure) world.
20 The buses are based on externally licensed IPs such as ARM NIC-301 and
27 - items:
28 - enum:
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| /kernel/linux/linux-5.10/drivers/staging/wfx/ |
| D | fwio.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2017-2020, Silicon Laboratories, Inc.
6 * Copyright (c) 2010, ST-Ericsson
92 return -ENOMEM; in sram_write_dma_safe()
111 wdev->pdata.file_fw, keyset_chip); in get_firmware()
112 ret = firmware_request_nowarn(fw, filename, wdev->dev); in get_firmware()
114 dev_info(wdev->dev, "can't load %s, falling back to %s.sec\n", in get_firmware()
115 filename, wdev->pdata.file_fw); in get_firmware()
117 wdev->pdata.file_fw); in get_firmware()
118 ret = request_firmware(fw, filename, wdev->dev); in get_firmware()
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| /kernel/linux/linux-4.19/drivers/crypto/caam/ |
| D | regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * CAAM hardware register-level view
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
16 * Architecture-specific register access methods
18 * CAAM's bus-addressable registers are 64 bits internally.
19 * They have been wired to be safely accessible on 32-bit
22 * can be treated as two 32-bit entities, or finally (c) if they
23 * must be treated as a single 64-bit value, then this can safely
24 * be done with two 32-bit cycles.
26 * For 32-bit operations on 64-bit values, CAAM follows the same
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra186-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
16 handles memory requests for 40-bit virtual addresses from internal clients
21 available for video and other secure applications, as well as DRAM ECC for
27 pattern: "^memory-controller@[0-9a-f]+$"
31 - enum:
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