| /kernel/linux/linux-5.10/arch/arm/mach-lpc32xx/ |
| D | suspend.S | 2 * arch/arm/mach-lpc32xx/suspend.S
41 stmfd r0!, {r3 - r7, sp, lr}
65 @ Setup self-refresh with support for manual exit of
66 @ self-refresh mode
72 @ Wait for self-refresh acknowledge, clocks to the DRAM device
73 @ will automatically stop on start of self-refresh
78 bne 3b @ Branch until self-refresh mode starts
80 @ Enter direct-run mode from run mode
115 @ Re-enter run mode with self-refresh flag cleared, but no DRAM
116 @ update yet. DRAM is still in self-refresh
[all …]
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| D | pm.c | 2 * arch/arm/mach-lpc32xx/pm.c
17 * direct-run, and halt modes. When switching between halt and run modes,
18 * the CPU transistions through direct-run mode. For Linux, direct-run
27 * Direct-run mode:
38 * wake the system up back into direct-run mode.
40 * DRAM refresh
41 * DRAM clocking and refresh are slightly different for systems with DDR
43 * SDRAM will still be accessible in direct-run mode. In DDR based systems,
44 * a transition to direct-run mode will stop all DDR accesses (no clocks).
46 * and exit DRAM self-refresh modes must not be executed in DRAM. A small
[all …]
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| /kernel/linux/linux-4.19/arch/arm/mach-lpc32xx/ |
| D | suspend.S | 2 * arch/arm/mach-lpc32xx/suspend.S
42 stmfd r0!, {r3 - r7, sp, lr}
66 @ Setup self-refresh with support for manual exit of
67 @ self-refresh mode
73 @ Wait for self-refresh acknowledge, clocks to the DRAM device
74 @ will automatically stop on start of self-refresh
79 bne 3b @ Branch until self-refresh mode starts
81 @ Enter direct-run mode from run mode
116 @ Re-enter run mode with self-refresh flag cleared, but no DRAM
117 @ update yet. DRAM is still in self-refresh
[all …]
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| D | pm.c | 2 * arch/arm/mach-lpc32xx/pm.c
17 * direct-run, and halt modes. When switching between halt and run modes,
18 * the CPU transistions through direct-run mode. For Linux, direct-run
27 * Direct-run mode:
38 * wake the system up back into direct-run mode.
40 * DRAM refresh
41 * DRAM clocking and refresh are slightly different for systems with DDR
43 * SDRAM will still be accessible in direct-run mode. In DDR based systems,
44 * a transition to direct-run mode will stop all DDR accesses (no clocks).
46 * and exit DRAM self-refresh modes must not be executed in DRAM. A small
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/ |
| D | drm_self_refresh_helper.c | 1 // SPDX-License-Identifier: MIT
27 * framework to implement panel self refresh (SR) support. Drivers are
31 * &drm_connector_state.self_refresh_aware to true at runtime if it is SR-aware
32 * (meaning it knows how to initiate self refresh on the panel).
38 * that tells you to disable/enable SR on the panel instead of power-cycling it.
72 struct drm_crtc *crtc = sr_data->crtc; in drm_self_refresh_helper_entry_work()
73 struct drm_device *dev = crtc->dev; in drm_self_refresh_helper_entry_work()
85 ret = -ENOMEM; in drm_self_refresh_helper_entry_work()
90 state->acquire_ctx = &ctx; in drm_self_refresh_helper_entry_work()
98 if (!crtc_state->enable) in drm_self_refresh_helper_entry_work()
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-socfpga/ |
| D | self-refresh.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2014-2015 Altera Corporation. All rights reserved.
32 .arch armv7-a
44 * return value: lower 16 bits: loop count going into self refresh
45 * upper 16 bits: loop count exiting self refresh
53 /* Enable self refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 1 */
89 /* Disable self-refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 0 */
109 * Shift loop count for exiting self refresh into upper 16 bits.
110 * Leave loop count for requesting self refresh in lower 16 bits.
125 .word . - socfpga_sdram_self_refresh
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| /kernel/linux/linux-4.19/arch/arm/mach-socfpga/ |
| D | self-refresh.S | 2 * Copyright (C) 2014-2015 Altera Corporation. All rights reserved.
43 .arch armv7-a
55 * return value: lower 16 bits: loop count going into self refresh
56 * upper 16 bits: loop count exiting self refresh
64 /* Enable self refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 1 */
100 /* Disable self-refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 0 */
120 * Shift loop count for exiting self refresh into upper 16 bits.
121 * Leave loop count for requesting self refresh in lower 16 bits.
136 .word . - socfpga_sdram_self_refresh
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| /kernel/linux/linux-4.19/arch/arm/mach-at91/ |
| D | pm_suspend.S | 2 * arch/arm/mach-at91/pm_slow_clock.S
17 #include "generated/at91_pm_data-offsets.h"
89 /* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */
93 stmfd sp!, {r4 - r12, lr}
119 /* Active the self-refresh mode */
143 /* Exit the self-refresh mode */
148 ldmfd sp!, {r4 - r12, pc}
192 /* Switch the main clock source to 12-MHz RC oscillator */
327 * @r0: 1 - active self-refresh mode
328 * 0 - exit self-refresh mode
[all …]
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| /kernel/linux/linux-4.19/arch/arm/mach-pxa/ |
| D | sleep.S | 2 * Low-level PXA250/210 sleep/wakeUp support
18 #include <mach/pxa2xx-regs.h>
27 * pxa3xx_finish_suspend() - forces CPU into sleep state (S2D3C4)
54 @ prepare SDRAM refresh settings
58 @ enable SDRAM self-refresh mode
61 @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
95 @ prepare SDRAM refresh settings
99 @ enable SDRAM self-refresh mode
106 @ We keep the change-down close to the actual suspend on SDRAM
107 @ as possible to eliminate messing about with the refresh clock
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-pxa/ |
| D | sleep.S | 2 * Low-level PXA250/210 sleep/wakeUp support
18 #include <mach/pxa2xx-regs.h>
27 * pxa3xx_finish_suspend() - forces CPU into sleep state (S2D3C4)
54 @ prepare SDRAM refresh settings
58 @ enable SDRAM self-refresh mode
61 @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
95 @ prepare SDRAM refresh settings
99 @ enable SDRAM self-refresh mode
106 @ We keep the change-down close to the actual suspend on SDRAM
107 @ as possible to eliminate messing about with the refresh clock
[all …]
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| /kernel/linux/linux-5.10/drivers/cpuidle/ |
| D | cpuidle-zynq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013 Xilinx
7 * based on arch/arm/mach-at91/cpuidle.c
9 * The cpu idle uses wait-for-interrupt and RAM self refresh in order
10 * to implement two idle states -
11 * #1 wait-for-interrupt
12 * #2 wait-for-interrupt and RAM self refresh
28 /* Add code for DDR self refresh start */ in zynq_enter_idle()
44 .desc = "WFI and RAM Self Refresh",
61 .name = "cpuidle-zynq",
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| /kernel/linux/linux-5.10/arch/sh/boards/mach-kfr2r09/ |
| D | sdram.S | 1 /* SPDX-License-Identifier: GPL-2.0
3 * KFR2R09 sdram self/auto-refresh setup code
11 #include <asm/asm-offsets.h>
13 #include <asm/romimage-macros.h>
15 /* code to enter and leave self-refresh. must be self-contained.
16 * this code will be copied to on-chip memory and executed from there.
21 /* DBSC: put memory in self-refresh mode */
37 /* DBSC: put memory in auto-refresh mode */
55 /* DBSC: re-initialize and put in auto-refresh */
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| /kernel/linux/linux-4.19/arch/sh/boards/mach-kfr2r09/ |
| D | sdram.S | 2 * KFR2R09 sdram self/auto-refresh setup code
14 #include <asm/asm-offsets.h>
16 #include <asm/romimage-macros.h>
18 /* code to enter and leave self-refresh. must be self-contained.
19 * this code will be copied to on-chip memory and executed from there.
24 /* DBSC: put memory in self-refresh mode */
40 /* DBSC: put memory in auto-refresh mode */
58 /* DBSC: re-initialize and put in auto-refresh */
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| /kernel/linux/linux-5.10/arch/sh/boards/mach-migor/ |
| D | sdram.S | 1 /* SPDX-License-Identifier: GPL-2.0
3 * Migo-R sdram self/auto-refresh setup code
11 #include <asm/asm-offsets.h>
13 #include <asm/romimage-macros.h>
15 /* code to enter and leave self-refresh. must be self-contained.
16 * this code will be copied to on-chip memory and executed from there.
21 /* SBSC: disable power down and put in self-refresh mode */
42 /* SBSC: set auto-refresh mode */
51 mov #-1, r4
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| /kernel/linux/linux-5.10/arch/sh/boards/mach-ap325rxa/ |
| D | sdram.S | 1 /* SPDX-License-Identifier: GPL-2.0
3 * AP325RXA sdram self/auto-refresh setup code
11 #include <asm/asm-offsets.h>
13 #include <asm/romimage-macros.h>
15 /* code to enter and leave self-refresh. must be self-contained.
16 * this code will be copied to on-chip memory and executed from there.
21 /* SBSC: disable power down and put in self-refresh mode */
42 /* SBSC: set auto-refresh mode */
51 mov #-1, r4
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| /kernel/linux/linux-4.19/arch/sh/boards/mach-migor/ |
| D | sdram.S | 2 * Migo-R sdram self/auto-refresh setup code
14 #include <asm/asm-offsets.h>
16 #include <asm/romimage-macros.h>
18 /* code to enter and leave self-refresh. must be self-contained.
19 * this code will be copied to on-chip memory and executed from there.
24 /* SBSC: disable power down and put in self-refresh mode */
45 /* SBSC: set auto-refresh mode */
54 mov #-1, r4
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| /kernel/linux/linux-4.19/arch/sh/boards/mach-ap325rxa/ |
| D | sdram.S | 2 * AP325RXA sdram self/auto-refresh setup code
14 #include <asm/asm-offsets.h>
16 #include <asm/romimage-macros.h>
18 /* code to enter and leave self-refresh. must be self-contained.
19 * this code will be copied to on-chip memory and executed from there.
24 /* SBSC: disable power down and put in self-refresh mode */
45 /* SBSC: set auto-refresh mode */
54 mov #-1, r4
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| /kernel/linux/linux-4.19/drivers/cpuidle/ |
| D | cpuidle-zynq.c | 2 * Copyright (C) 2012-2013 Xilinx
6 * based on arch/arm/mach-at91/cpuidle.c
20 * The cpu idle uses wait-for-interrupt and RAM self refresh in order
21 * to implement two idle states -
22 * #1 wait-for-interrupt
23 * #2 wait-for-interrupt and RAM self refresh
39 /* Add code for DDR self refresh start */ in zynq_enter_idle()
55 .desc = "WFI and RAM Self Refresh",
72 .name = "cpuidle-zynq",
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/devfreq/ |
| D | rk3399_dmc.txt | 4 - compatible: Must be "rockchip,rk3399-dmc".
5 - devfreq-events: Node to get DDR loading, Refer to
7 rockchip-dfi.txt
8 - clocks: Phandles for clock specified in "clock-names" property
9 - clock-names : The name of clock used by the DFI, must be
11 - operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp.txt
13 - center-supply: DMC supply node.
14 - status: Marks the node enabled/disabled.
17 - interrupts: The CPU interrupt number. The interrupt specifier
21 - rockchip,pmu: Phandle to the syscon managing the "PMU general register
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/devfreq/ |
| D | rk3399_dmc.txt | 4 - compatible: Must be "rockchip,rk3399-dmc".
5 - devfreq-events: Node to get DDR loading, Refer to
7 rockchip-dfi.txt
8 - clocks: Phandles for clock specified in "clock-names" property
9 - clock-names : The name of clock used by the DFI, must be
11 - operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp.txt
13 - center-supply: DMC supply node.
14 - status: Marks the node enabled/disabled.
17 - interrupts: The CPU interrupt number. The interrupt specifier
24 - rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/rk3399-ddr.h,
[all …]
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| /kernel/linux/linux-5.10/arch/sh/boards/mach-ecovec24/ |
| D | sdram.S | 1 /* SPDX-License-Identifier: GPL-2.0
3 * Ecovec24 sdram self/auto-refresh setup code
11 #include <asm/asm-offsets.h>
13 #include <asm/romimage-macros.h>
15 /* code to enter and leave self-refresh. must be self-contained.
16 * this code will be copied to on-chip memory and executed from there.
21 /* DBSC: put memory in self-refresh mode */
41 /* DBSC: put memory in auto-refresh mode */
55 /* DBSC: re-initialize and put in auto-refresh */
|
| /kernel/linux/linux-4.19/arch/sh/boards/mach-ecovec24/ |
| D | sdram.S | 2 * Ecovec24 sdram self/auto-refresh setup code
14 #include <asm/asm-offsets.h>
16 #include <asm/romimage-macros.h>
18 /* code to enter and leave self-refresh. must be self-contained.
19 * this code will be copied to on-chip memory and executed from there.
24 /* DBSC: put memory in self-refresh mode */
44 /* DBSC: put memory in auto-refresh mode */
58 /* DBSC: re-initialize and put in auto-refresh */
|
| /kernel/linux/linux-5.10/arch/sh/kernel/cpu/shmobile/ |
| D | pm.c | 1 // SPDX-License-Identifier: GPL-2.0
28 * Sleep Self-Refresh mode is above plus RAM put in Self-Refresh
29 * Standby Self-Refresh mode is above plus stopped clocks
37 * U-standby mode is unsupported since it needs bootloader hacks
62 /* Let assembly snippet in on-chip memory handle the rest */ in sh_mobile_call_standby()
88 sdp->addr.stbcr = 0xa4150020; /* STBCR */ in sh_mobile_register_self_refresh()
89 sdp->addr.bar = 0xa4150040; /* BAR */ in sh_mobile_register_self_refresh()
90 sdp->addr.pteh = 0xff000000; /* PTEH */ in sh_mobile_register_self_refresh()
91 sdp->addr.ptel = 0xff000004; /* PTEL */ in sh_mobile_register_self_refresh()
92 sdp->addr.ttb = 0xff000008; /* TTB */ in sh_mobile_register_self_refresh()
[all …]
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| /kernel/linux/linux-5.10/arch/sh/boards/mach-se/7724/ |
| D | sdram.S | 1 /* SPDX-License-Identifier: GPL-2.0
3 * MS7724SE sdram self/auto-refresh setup code
11 #include <asm/asm-offsets.h>
13 #include <asm/romimage-macros.h>
15 /* code to enter and leave self-refresh. must be self-contained.
16 * this code will be copied to on-chip memory and executed from there.
21 /* DBSC: put memory in self-refresh mode */
37 /* DBSC: put memory in auto-refresh mode */
72 /* DBSC: re-initialize and put in auto-refresh */
|
| /kernel/linux/linux-4.19/arch/sh/kernel/cpu/shmobile/ |
| D | pm.c | 31 * Sleep Self-Refresh mode is above plus RAM put in Self-Refresh
32 * Standby Self-Refresh mode is above plus stopped clocks
40 * U-standby mode is unsupported since it needs bootloader hacks
65 /* Let assembly snippet in on-chip memory handle the rest */ in sh_mobile_call_standby()
91 sdp->addr.stbcr = 0xa4150020; /* STBCR */ in sh_mobile_register_self_refresh()
92 sdp->addr.bar = 0xa4150040; /* BAR */ in sh_mobile_register_self_refresh()
93 sdp->addr.pteh = 0xff000000; /* PTEH */ in sh_mobile_register_self_refresh()
94 sdp->addr.ptel = 0xff000004; /* PTEL */ in sh_mobile_register_self_refresh()
95 sdp->addr.ttb = 0xff000008; /* TTB */ in sh_mobile_register_self_refresh()
96 sdp->addr.tea = 0xff00000c; /* TEA */ in sh_mobile_register_self_refresh()
[all …]
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