Searched full:setings (Results 1 – 4 of 4) sorted by relevance
113 Pull up setings for 2 pull resistors, R0 and R1. User can
140 * Compute the correct order setings to ensure that an overlapping blit
128 * Compute the correct order setings to ensure that an overlapping blit
241 /* We could not modify IRQ setings: clear new configuration */ in vfio_ap_irq_enable()