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| /kernel/linux/linux-4.19/Documentation/x86/ |
| D | topology.txt | 8 The architecture-agnostic topology definitions are in
9 Documentation/cputopology.txt. This file holds x86-specific
14 Needless to say, code should use the generic functions - this file is *only*
25 the past a socket always contained a single package (see below), but with the
32 - packages
33 - cores
34 - threads
43 Package-related topology information in the kernel:
45 - cpuinfo_x86.x86_max_cores:
49 - cpuinfo_x86.phys_proc_id:
[all …]
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| /kernel/linux/linux-5.10/Documentation/x86/ |
| D | topology.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 The architecture-agnostic topology definitions are in
12 Documentation/admin-guide/cputopology.rst. This file holds x86-specific
17 Needless to say, code should use the generic functions - this file is *only*
28 the past a socket always contained a single package (see below), but with the
35 - packages
36 - cores
37 - threads
48 Package-related topology information in the kernel:
50 - cpuinfo_x86.x86_max_cores:
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/omap/ |
| D | ctrl.txt | 11 [1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
15 - compatible: Must be one of:
16 "ti,am3-scm"
17 "ti,am4-scm"
18 "ti,dm814-scrm"
19 "ti,dm816-scrm"
20 "ti,omap2-scm"
21 "ti,omap3-scm"
22 "ti,omap4-scm-core"
23 "ti,omap4-scm-padconf-core"
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/omap/ |
| D | ctrl.txt | 11 [1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
15 - compatible: Must be one of:
16 "ti,am3-scm"
17 "ti,am4-scm"
18 "ti,dm814-scrm"
19 "ti,dm816-scrm"
20 "ti,omap2-scm"
21 "ti,omap3-scm"
22 "ti,omap4-scm-core"
23 "ti,omap4-scm-padconf-core"
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,c64x+megamod-pic.txt | 2 -------------------
4 * C64X+ Core Interrupt Controller
6 The core interrupt controller provides 16 prioritized interrupts to the
7 C64X+ core. Priority 0 and 1 are used for reset and NMI respectively.
8 Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
9 sources coming from outside the core.
12 --------------------
13 - compatible: Should be "ti,c64x+core-pic";
14 - #interrupt-cells: <1>
17 ------------------------------
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,c64x+megamod-pic.txt | 2 -------------------
4 * C64X+ Core Interrupt Controller
6 The core interrupt controller provides 16 prioritized interrupts to the
7 C64X+ core. Priority 0 and 1 are used for reset and NMI respectively.
8 Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
9 sources coming from outside the core.
12 --------------------
13 - compatible: Should be "ti,c64x+core-pic";
14 - #interrupt-cells: <1>
17 ------------------------------
[all …]
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| /kernel/linux/linux-4.19/Documentation/driver-api/ |
| D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
32 A physical connector on the motherboard that accepts a single memory
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
45 same branch can be used in single mode or in lockstep mode. When
50 of correcting more errors than on single mode.
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
[all …]
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| /kernel/linux/linux-5.10/Documentation/driver-api/ |
| D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
32 A physical connector on the motherboard that accepts a single memory
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
45 same branch can be used in single mode or in lockstep mode. When
50 of correcting more errors than on single mode.
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
[all …]
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| D | xillybus.rst | 10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
21 -- Pipe attributes
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/iio/adc/ |
| D | st,stm32-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 STM32 ADC is a successive approximation analog-to-digital converter.
12 in single, continuous, scan or discontinuous mode. Result of the ADC is
13 stored in a left-aligned or right-aligned 32-bit data register.
17 voltage goes beyond the user-defined, higher or lower thresholds.
22 - Fabrice Gasnier <fabrice.gasnier@st.com>
27 - st,stm32f4-adc-core
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/iio/adc/ |
| D | st,stm32-adc.txt | 3 STM32 ADC is a successive approximation analog-to-digital converter.
5 in single, continuous, scan or discontinuous mode. Result of the ADC is
6 stored in a left-aligned or right-aligned 32-bit data register.
10 voltage goes beyond the user-defined, higher or lower thresholds.
16 - regular conversion can be done in sequence, running in background
17 - injected conversions have higher priority, and so have the ability to
22 -----------------------------------
24 - compatible: Should be one of:
25 "st,stm32f4-adc-core"
26 "st,stm32h7-adc-core"
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/ |
| D | example-schema.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 # All the top-level keys are standard json-schema keywords except for
10 $id: http://devicetree.org/schemas/example-schema.yaml#
11 # $schema is the meta-schema this schema should be validated with.
12 $schema: http://devicetree.org/meta-schemas/core.yaml#
17 - Rob Herring <robh@kernel.org>
20 A more detailed multi-line description of the binding.
44 - items:
51 - enum:
[all …]
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| D | trivial-devices.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
28 - enum:
29 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
30 - ad,ad7414
31 # ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems
32 - ad,adm9240
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | pistachio-clock.txt | 4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
6 from the device-tree.
9 ----------------
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
17 Core clock controller:
18 ----------------------
20 The core clock controller generates clocks for the CPU, RPU (WiFi + BT
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/ |
| D | pistachio-clock.txt | 4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
6 from the device-tree.
9 ----------------
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
17 Core clock controller:
18 ----------------------
20 The core clock controller generates clocks for the CPU, RPU (WiFi + BT
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/ |
| D | trivial-devices.txt | 12 abracon,abb5zes3 AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface
13 ad,ad7414 SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature …
14 ad,adm9240 ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems
15 adi,adt7461 +/-1C TDM Extended Temp Range I.C
16 adt7461 +/-1C TDM Extended Temp Range I.C
17 adi,adt7473 +/-1C TDM Extended Temp Range I.C
18 adi,adt7475 +/-1C TDM Extended Temp Range I.C
19 adi,adt7476 +/-1C TDM Extended Temp Range I.C
20 adi,adt7490 +/-1C TDM Extended Temp Range I.C
21 adi,adxl345 Three-Axis Digital Accelerometer
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
17 The bottom hierarchy level sits at core or thread level depending on whether
18 symmetric multi-threading (SMT) is supported or not.
23 in the system and map to the hierarchy level "core" above.
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
39 2 - cpu-map node
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/ |
| D | i2c.txt | 8 -----------------------------
10 - #address-cells - should be <1>. Read more about addresses below.
11 - #size-cells - should be <0>.
12 - compatible - name of I2C bus controller
18 are described by a single value.
21 -----------------------------
26 - clock-frequency
29 - i2c-bus
31 devices and non-I2C devices, the 'i2c-bus' subnode can be used for
32 populating I2C devices. If the 'i2c-bus' subnode is present, only
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/spmi/ |
| D | qcom,spmi-pmic-arb.txt | 4 controller with wrapping arbitration logic to allow for multiple on-chip
5 devices to control a single SPMI master.
13 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
17 - compatible : should be "qcom,spmi-pmic-arb".
18 - reg-names : must contain:
19 "core" - core registers
20 "intr" - interrupt controller registers
21 "cnfg" - configuration registers
23 "chnls" - tx-channel per virtual slave registers.
24 "obsrvr" - rx-channel (called observer) per virtual slave registers.
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/spmi/ |
| D | qcom,spmi-pmic-arb.txt | 4 controller with wrapping arbitration logic to allow for multiple on-chip
5 devices to control a single SPMI master.
13 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
17 - compatible : should be "qcom,spmi-pmic-arb".
18 - reg-names : must contain:
19 "core" - core registers
20 "intr" - interrupt controller registers
21 "cnfg" - configuration registers
23 "chnls" - tx-channel per virtual slave registers.
24 "obsrvr" - rx-channel (called observer) per virtual slave registers.
[all …]
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| /kernel/linux/linux-4.19/Documentation/networking/ |
| D | cxgb.txt | 30 Adaptive Interrupts (adaptive-rx)
31 ---------------------------------
41 By default, adaptive-rx is disabled.
42 To enable adaptive-rx:
44 ethtool -C <interface> adaptive-rx on
46 To disable adaptive-rx, use ethtool:
48 ethtool -C <interface> adaptive-rx off
50 After disabling adaptive-rx, the timer latency value will be set to 50us.
51 You may set the timer latency after disabling adaptive-rx:
53 ethtool -C <interface> rx-usecs <microseconds>
[all …]
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| /kernel/linux/linux-5.10/include/media/ |
| D | tuner.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * tuner.h - definition for different tuners
5 * Copyright (C) 1997 Markus Schroeder (schroedm@uni-duesseldorf.de)
6 * minor modifications by Ralph Metzler (rjkm@thp.uni-koeln.de)
14 #include <media/v4l2-mc.h>
73 #define TUNER_PHILIPS_4IN1 44 /* ATI TV Wonder Pro - Conexant */
83 #define TUNER_MICROTUNE_4042FI5 49 /* DViCO FusionHDTV 3 Gold-Q - 4042 FI5 (3X 8147) */
90 #define TUNER_TCL_2002MB 55 /* Hauppauge PVR-150 PAL */
92 #define TUNER_PHILIPS_FQ1216AME_MK4 56 /* Hauppauge PVR-150 PAL */
93 #define TUNER_PHILIPS_FQ1236A_MK4 57 /* Hauppauge PVR-500MCE NTSC */
[all …]
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| /kernel/linux/linux-5.10/arch/c6x/include/asm/ |
| D | irq.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/radix-tree.h>
22 * The C64X+ core has 16 IRQ vectors. One each is used by Reset and NMI. Two
28 * single core IRQ vector. There are four combined sources, each of which
30 * can each route a single SoC interrupt directly.
|
| /kernel/linux/linux-4.19/Documentation/arm/Marvell/ |
| D | README | 12 ------------
19 …asheet : http://www.embeddedarm.com/documentation/third-party/MV88F5182-datasheet.pdf
20 …'s User Guide : http://www.embeddedarm.com/documentation/third-party/MV88F5182-opensource-manual.p…
21 … Manual : http://www.embeddedarm.com/documentation/third-party/MV88F5182-usermanual.pdf
25 Core: Feroceon 88fr331 (88f51xx) or 88fr531-vd (88f52xx) ARMv5 compatible
26 Linux kernel mach directory: arch/arm/mach-orion5x
27 Linux kernel plat directory: arch/arm/plat-orion
30 ---------------
34 … Product Brief : http://www.marvell.com/embedded-processors/armada-300/assets/armada_310.pdf
36 … Product Brief : http://www.marvell.com/embedded-processors/armada-300/assets/armada_310.pdf
[all …]
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| /kernel/linux/linux-4.19/Documentation/ |
| D | xillybus.txt | 10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
21 -- Pipe attributes
[all …]
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