| /kernel/linux/linux-5.10/drivers/mtd/spi-nor/ |
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
3 spi-nor-objs := core.o sfdp.o
4 spi-nor-objs += atmel.o
5 spi-nor-objs += catalyst.o
6 spi-nor-objs += eon.o
7 spi-nor-objs += esmt.o
8 spi-nor-objs += everspin.o
9 spi-nor-objs += fujitsu.o
10 spi-nor-objs += gigadevice.o
11 spi-nor-objs += intel.o
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| D | core.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
48 /* Dual SPI */
54 /* Quad SPI */
60 /* Octal SPI */
72 /* Quad SPI */
77 /* Octal SPI */
86 * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type
92 * @opcode: the SPI command op code to erase the sector/block.
107 * struct spi_nor_erase_command - Used for non-uniform erases
110 * are run-length encoded.
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| D | core.c | 1 // SPDX-License-Identifier: GPL-2.0
22 #include <linux/spi/flash.h>
23 #include <linux/mtd/spi-nor.h>
30 * For everything but full-chip erase; probably could be much smaller, but kept
36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
44 * spi_nor_spimem_bounce() - check if a bounce buffer is needed for the data
46 * @nor: pointer to 'struct spi_nor'
53 static bool spi_nor_spimem_bounce(struct spi_nor *nor, struct spi_mem_op *op) in spi_nor_spimem_bounce() argument
55 /* op->data.buf.in occupies the same memory as op->data.buf.out */ in spi_nor_spimem_bounce()
56 if (object_is_on_stack(op->data.buf.in) || in spi_nor_spimem_bounce()
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| /kernel/linux/linux-4.19/drivers/mtd/spi-nor/ |
| D | Kconfig | 2 tristate "SPI-NOR device support"
5 This is the framework for the SPI NOR which can be used by the SPI
6 device drivers and the SPI-NOR device driver.
11 tristate "Mediatek MT81xx SPI NOR flash controller"
14 This enables access to SPI NOR flash, using MT81xx SPI NOR flash
15 controller. This controller does not support generic SPI BUS, it only
16 supports SPI NOR Flash.
33 tristate "Aspeed flash controllers in SPI mode"
38 in the Aspeed AST2500/AST2400 SoCs when attached to SPI NOR chips,
39 and support for the SPI flash memory controller (SPI) for
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| D | nxp-spifi.c | 2 * SPI-NOR driver for NXP SPI Flash Interface (SPIFI)
22 #include <linux/mtd/spi-nor.h>
26 #include <linux/spi/spi.h>
63 struct spi_nor nor; member
73 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_wait_for_cmd()
76 dev_warn(spifi->dev, "command timed out\n"); in nxp_spifi_wait_for_cmd()
86 writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT); in nxp_spifi_reset()
87 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_reset()
90 dev_warn(spifi->dev, "state reset timed out\n"); in nxp_spifi_reset()
99 if (!spifi->memory_mode) in nxp_spifi_set_memory_mode_off()
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| D | aspeed-smc.c | 4 * Copyright (c) 2015-2016, IBM Corporation.
19 #include <linux/mtd/spi-nor.h>
25 #define DEVICE_NAME "aspeed-smc"
28 * The driver only support SPI flash
104 struct spi_nor nor; member
113 void __iomem *ahb_base; /* per-chip windows resource */
120 * SPI Flash Configuration Register (AST2500 SPI)
123 * CE0 and CE1 can only be of type SPI. CE2 can be of type NOR but the
160 #define CONTROL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI */
190 * and the end address of the mapping window of a flash SPI slave :
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| /kernel/linux/linux-4.19/drivers/mtd/devices/ |
| D | m25p80.c | 2 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips
26 #include <linux/spi/spi.h>
27 #include <linux/spi/spi-mem.h>
28 #include <linux/spi/flash.h>
29 #include <linux/mtd/spi-nor.h>
36 static int m25p80_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len) in m25p80_read_reg() argument
38 struct m25p *flash = nor->priv; in m25p80_read_reg()
48 return -ENOMEM; in m25p80_read_reg()
51 ret = spi_mem_exec_op(flash->spimem, &op); in m25p80_read_reg()
53 dev_err(&flash->spimem->spi->dev, "error %d reading %x\n", ret, in m25p80_read_reg()
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| /kernel/linux/linux-5.10/Documentation/driver-api/mtd/ |
| D | spi-nor.rst | 2 SPI NOR framework
5 Part I - Why do we need this framework?
6 ---------------------------------------
8 SPI bus controllers (drivers/spi/) only deal with streams of bytes; the bus
11 arbitrary streams of bytes, but rather are designed specifically for SPI NOR.
13 In particular, Freescale's QuadSPI controller must know the NOR commands to
14 find the right LUT sequence. Unfortunately, the SPI subsystem has no notion of
15 opcodes, addresses, or data payloads; a SPI controller simply knows to send or
18 details of the SPI NOR protocol.
20 Part II - How does the framework work?
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/ |
| D | mediatek,spi-mtk-nor.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Serial NOR flash controller for MediaTek ARM SoCs
10 - Bayi Cheng <bayi.cheng@mediatek.com>
11 - Chuanhong Guo <gch981213@gmail.com>
14 This spi controller support single, dual, or quad mode transfer for
15 SPI NOR flash. There should be only one spi slave device following
16 generic spi bindings. It's not recommended to use this controller
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| /kernel/linux/linux-4.19/Documentation/mtd/ |
| D | spi-nor.txt | 1 SPI NOR framework
4 Part I - Why do we need this framework?
5 ---------------------------------------
7 SPI bus controllers (drivers/spi/) only deal with streams of bytes; the bus
10 arbitrary streams of bytes, but rather are designed specifically for SPI NOR.
12 In particular, Freescale's QuadSPI controller must know the NOR commands to
13 find the right LUT sequence. Unfortunately, the SPI subsystem has no notion of
14 opcodes, addresses, or data payloads; a SPI controller simply knows to send or
17 details of the SPI NOR protocol.
19 Part II - How does the framework work?
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mtd/ |
| D | mtk-quadspi.txt | 1 * Serial NOR flash controller for MTK MT81xx (and similar)
4 - compatible: For mt8173, compatible should be "mediatek,mt8173-nor",
6 For every other SoC, should contain both the SoC-specific compatible
7 string and "mediatek,mt8173-nor".
9 "mediatek,mt2701-nor", "mediatek,mt8173-nor"
10 "mediatek,mt2712-nor", "mediatek,mt8173-nor"
11 "mediatek,mt7622-nor", "mediatek,mt8173-nor"
12 "mediatek,mt7623-nor", "mediatek,mt8173-nor"
13 "mediatek,mt8173-nor"
14 - reg: physical base address and length of the controller's register
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| D | hisilicon,fmc-spi-nor.txt | 1 HiSilicon SPI-NOR Flash Controller
4 - compatible : Should be "hisilicon,fmc-spi-nor" and one of the following strings:
5 "hisilicon,hi3519-spi-nor"
6 - address-cells : Should be 1.
7 - size-cells : Should be 0.
8 - reg : Offset and length of the register set for the controller device.
9 - reg-names : Must include the following two entries: "control", "memory".
10 - clocks : handle to spi-nor flash controller clock.
13 spi-nor-controller@10000000 {
14 compatible = "hisilicon,hi3519-spi-nor", "hisilicon,fmc-spi-nor";
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| D | aspeed-smc.txt | 2 * Aspeed SPI Flash Memory Controller
5 three chip selects, two of which are always of SPI type and the third
6 can be SPI or NOR type flash. These bindings only describe SPI.
8 The two SPI flash memory controllers in the AST2500 each support two
12 - compatible : Should be one of
13 "aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller
14 "aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller
15 "aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller
16 "aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers
18 - reg : the first contains the control register location and length,
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| /kernel/linux/linux-5.10/include/linux/mtd/ |
| D | spi-nor.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
12 #include <linux/spi/spi-mem.h>
19 * requires a 4-byte (32-bit) address.
31 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
32 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
33 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
34 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
35 #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
36 #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
55 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
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| /kernel/linux/linux-4.19/include/linux/mtd/ |
| D | spi-nor.h | 26 #define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */
37 * requires a 4-byte (32-bit) address.
48 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
49 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
50 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
51 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
68 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
71 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
72 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
73 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | hisilicon,fmc-spi-nor.txt | 1 HiSilicon SPI-NOR Flash Controller
4 - compatible : Should be "hisilicon,fmc-spi-nor" and one of the following strings:
5 "hisilicon,hi3519-spi-nor"
6 - address-cells : Should be 1.
7 - size-cells : Should be 0.
8 - reg : Offset and length of the register set for the controller device.
9 - reg-names : Must include the following two entries: "control", "memory".
10 - clocks : handle to spi-nor flash controller clock.
13 spi-nor-controller@10000000 {
14 compatible = "hisilicon,hi3519-spi-nor", "hisilicon,fmc-spi-nor";
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| D | aspeed-smc.txt | 2 * Aspeed SPI Flash Memory Controller
5 three chip selects, two of which are always of SPI type and the third
6 can be SPI or NOR type flash. These bindings only describe SPI.
8 The two SPI flash memory controllers in the AST2500 each support two
12 - compatible : Should be one of
13 "aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller
14 "aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller
15 "aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller
16 "aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers
18 - reg : the first contains the control register location and length,
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls1028a-qds.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
29 stdout-path = "serial0:115200n8";
37 sys_mclk: clock-mclk {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <25000000>;
43 reg_1p8v: regulator-1p8v {
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| D | fsl-ls1088a-qds.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
21 bus-num = <0>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "jedec,spi-nor";
29 spi-max-frequency = <1000000>;
33 #address-cells = <1>;
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| D | fsl-ls1046a-qds.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
11 /dts-v1/;
13 #include "fsl-ls1046a.dtsi"
17 compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
31 stdout-path = "serial0:115200n8";
36 bus-num = <0>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "n25q128a11", "jedec,spi-nor";
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| /kernel/linux/linux-5.10/drivers/mtd/spi-nor/controllers/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Aspeed flash controllers in SPI mode"
8 in the Aspeed AST2500/AST2400 SoCs when attached to SPI NOR chips,
9 and support for the SPI flash memory controller (SPI) for
10 the host firmware. The implementation only supports SPI NOR.
13 tristate "Hisilicon FMC SPI NOR Flash Controller(SFC)"
17 This enables support for HiSilicon FMC SPI NOR flash controller.
20 tristate "NXP SPI Flash Interface (SPIFI)"
24 Enable support for the NXP LPC SPI Flash Interface controller.
26 SPIFI is a specialized controller for connecting serial SPI
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| D | nxp-spifi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI NOR driver for NXP SPI Flash Interface (SPIFI)
18 #include <linux/mtd/spi-nor.h>
22 #include <linux/spi/spi.h>
59 struct spi_nor nor; member
69 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_wait_for_cmd()
72 dev_warn(spifi->dev, "command timed out\n"); in nxp_spifi_wait_for_cmd()
82 writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT); in nxp_spifi_reset()
83 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_reset()
86 dev_warn(spifi->dev, "state reset timed out\n"); in nxp_spifi_reset()
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| D | aspeed-smc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2015-2016, IBM Corporation.
15 #include <linux/mtd/spi-nor.h>
21 #define DEVICE_NAME "aspeed-smc"
24 * The driver only support SPI flash
100 struct spi_nor nor; member
109 void __iomem *ahb_base; /* per-chip windows resource */
116 * SPI Flash Configuration Register (AST2500 SPI)
119 * CE0 and CE1 can only be of type SPI. CE2 can be of type NOR but the
156 #define CONTROL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI */
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/ |
| D | mpc8536ds.dtsi | 2 * MPC8536DS Device Tree Source stub (no addresses or top-level ranges)
13 * * Neither the name of Freescale Semiconductor nor the
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 label = "ramdisk-nor";
51 label = "diagnostic-nor";
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| /kernel/linux/linux-4.19/arch/powerpc/boot/dts/fsl/ |
| D | mpc8536ds.dtsi | 2 * MPC8536DS Device Tree Source stub (no addresses or top-level ranges)
13 * * Neither the name of Freescale Semiconductor nor the
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 label = "ramdisk-nor";
51 label = "diagnostic-nor";
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