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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sram/
Dsram.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sram/sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
15 Each child of the sram node specifies a region of reserved memory. Each
19 Following the generic-names recommended practice, node names should
25 pattern: "^sram(@.*)?"
30 - mmio-sram
[all …]
Dallwinner,sun4i-a10-system-control.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The SRAM controller found on most Allwinner devices is represented
15 by a regular node for the SRAM controller itself, with sub-nodes
16 representing the SRAM handled by the SRAM controller.
19 "#address-cells":
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/sram/
Dsunxi-sram.txt1 Allwinnner SoC SRAM controllers
2 -----------------------------------------------------
4 The SRAM controller found on most Allwinner devices is represented by
5 a regular node for the SRAM controller itself, with sub-nodes
6 reprensenting the SRAM handled by the SRAM controller.
9 ---------------
12 - compatible : should be:
13 - "allwinner,sun4i-a10-sram-controller" (deprecated)
14 - "allwinner,sun4i-a10-system-control"
15 - "allwinner,sun5i-a13-system-control"
[all …]
Drockchip-smp-sram.txt1 Rockchip SRAM for smp bringup:
2 ------------------------------
4 Rockchip's smp-capable SoCs use the first part of the sram for the bringup
6 residing at the very beginning of the sram.
8 Therefore a reserved section sub-node has to be added to the mmio-sram
11 Required sub-node properties:
12 - compatible : should be "rockchip,rk3066-smp-sram"
14 The rest of the properties should follow the generic mmio-sram discription
15 found in Documentation/devicetree/bindings/sram/sram.txt
19 sram: sram@10080000 {
[all …]
Dsamsung-sram.txt2 ------------------------------------
4 Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
8 Therefore reserved section sub-nodes have to be added to the mmio-sram
10 non-secure execution environment.
12 Required sub-node properties:
13 - compatible : depending upon boot mode, should be
14 "samsung,exynos4210-sysram" : for Secure SYSRAM
15 "samsung,exynos4210-sysram-ns" : for Non-secure SYSRAM
17 The rest of the properties should follow the generic mmio-sram discription
18 found in Documentation/devicetree/bindings/sram/sram.txt
[all …]
/kernel/liteos_a/kernel/include/
Dlos_builddef.h2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
55 #define LITE_OS_SEC_TEXT /* __attribute__((section(".text.sram"))) */
59 #define LITE_OS_SEC_TEXT_MINOR /* __attribute__((section(".text.ddr"))) */
63 #define LITE_OS_SEC_TEXT_INIT /* __attribute__((section(".text.init"))) */
67 #define LITE_OS_SEC_DATA /* __attribute__((section(".data.sram"))) */
71 #define LITE_OS_SEC_DATA_MINOR /* __attribute__((section(".data.ddr"))) */
75 #define LITE_OS_SEC_DATA_INIT /* __attribute__((section(".data.init"))) */
79 #define LITE_OS_SEC_BSS /* __attribute__((section(".bss.sram"))) */
83 #define LITE_OS_SEC_BSS_MINOR /* __attribute__((section(".bss.ddr"))) */
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/amlogic/
Dsmp-sram.txt1 Amlogic Meson8 and Meson8b SRAM for smp bringup:
2 ------------------------------------------------
4 Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
8 Therefore a reserved section sub-node has to be added to the mmio-sram
11 Required sub-node properties:
12 - compatible : depending on the SoC this should be one of:
13 "amlogic,meson8-smp-sram"
14 "amlogic,meson8b-smp-sram"
16 The rest of the properties should follow the generic mmio-sram discription
17 found in ../../misc/sram.txt
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/sunxi/
Dsmp-sram.txt1 Allwinner SRAM for smp bringup:
2 ------------------------------------------------
4 Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
9 Therefore a reserved section sub-node has to be added to the mmio-sram
12 Note that this is separate from the Allwinner SRAM controller found in
13 ../../sram/sunxi-sram.txt. This SRAM is secure only and not mappable to
16 Also there are no "secure-only" properties. The implementation should
17 check if this SRAM is usable first.
19 Required sub-node properties:
20 - compatible : depending on the SoC this should be one of:
[all …]
/kernel/liteos_m/utils/
Dlos_compiler.h2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
202 * Vector table section
205 #define LITE_OS_SEC_VEC __attribute__ ((section(".vector")))
210 * .Text section (Code section)
213 #define LITE_OS_SEC_TEXT // __attribute__((section(".sram.text")))
218 * .Text.ddr section
221 #define LITE_OS_SEC_TEXT_MINOR // __attribute__((section(".dyn.text")))
226 * .Text.init section
229 #define LITE_OS_SEC_TEXT_INIT // __attribute__((section(".dyn.text")))
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dsuniv-f1c100s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&intc>;
13 osc24M: clk-24M {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <24000000>;
17 clock-output-names = "osc24M";
20 osc32k: clk-32k {
[all …]
Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/clock/sun5i-ccu.h>
46 #include <dt-bindings/dma/sun4i-a10.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
50 interrupt-parent = <&intc>;
51 #address-cells = <1>;
52 #size-cells = <1>;
55 #address-cells = <1>;
[all …]
Dsun8i-h3.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include "sunxi-h3-h5.dtsi"
44 #include <dt-bindings/thermal/thermal.h>
48 compatible = "operating-points-v2";
49 opp-shared;
51 opp-648000000 {
52 opp-hz = /bits/ 64 <648000000>;
53 opp-microvolt = <1040000 1040000 1300000>;
54 clock-latency-ns = <244144>; /* 8 32k periods */
57 opp-816000000 {
[all …]
Dsun4i-a10.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/thermal/thermal.h>
45 #include <dt-bindings/dma/sun4i-a10.h>
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #address-cells = <1>;
51 #size-cells = <1>;
52 interrupt-parent = <&intc>;
59 #address-cells = <1>;
60 #size-cells = <1>;
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/clock/sun5i-ccu.h>
48 #include <dt-bindings/dma/sun4i-a10.h>
49 #include <dt-bindings/reset/sun5i-ccu.h>
52 interrupt-parent = <&intc>;
55 #address-cells = <1>;
56 #size-cells = <0>;
60 compatible = "arm,cortex-a8";
[all …]
Dsun8i-h3.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include "sunxi-h3-h5.dtsi"
47 compatible = "operating-points-v2";
48 opp-shared;
50 opp-648000000 {
51 opp-hz = /bits/ 64 <648000000>;
52 opp-microvolt = <1040000 1040000 1300000>;
53 clock-latency-ns = <244144>; /* 8 32k periods */
56 opp-816000000 {
57 opp-hz = /bits/ 64 <816000000>;
[all …]
Dsun7i-a20.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
49 #include <dt-bindings/dma/sun4i-a10.h>
50 #include <dt-bindings/clock/sun7i-a20-ccu.h>
51 #include <dt-bindings/reset/sun4i-a10-ccu.h>
54 interrupt-parent = <&gic>;
61 #address-cells = <1>;
62 #size-cells = <1>;
[all …]
/kernel/linux/linux-5.10/drivers/memory/
Dti-emif-pm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI AM33XX SRAM EMIF Driver
5 * Copyright (C) 2016-2017 Texas Instruments Inc.
17 #include <linux/sram.h>
18 #include <linux/ti-emif-sram.h>
22 #define TI_EMIF_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
43 return (emif_data->ti_emif_sram_virt + in sram_suspend_address()
50 return ((unsigned long)emif_data->ti_emif_sram_phys + in sram_resume_address()
56 gen_pool_free(emif_data->sram_pool_code, emif_data->ti_emif_sram_virt, in ti_emif_free_sram()
58 gen_pool_free(emif_data->sram_pool_data, in ti_emif_free_sram()
[all …]
/kernel/linux/linux-4.19/drivers/memory/
Dti-emif-pm.c2 * TI AM33XX SRAM EMIF Driver
4 * Copyright (C) 2016-2017 Texas Instruments Inc.
25 #include <linux/sram.h>
26 #include <linux/ti-emif-sram.h>
30 #define TI_EMIF_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
51 return (emif_data->ti_emif_sram_virt + in sram_suspend_address()
58 return ((unsigned long)emif_data->ti_emif_sram_phys + in sram_resume_address()
64 gen_pool_free(emif_data->sram_pool_code, emif_data->ti_emif_sram_virt, in ti_emif_free_sram()
66 gen_pool_free(emif_data->sram_pool_data, in ti_emif_free_sram()
67 emif_data->ti_emif_sram_data_virt, in ti_emif_free_sram()
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-h5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <arm/sunxi-h3-h5.dtsi>
6 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <0>;
14 compatible = "arm,cortex-a53";
17 enable-method = "psci";
19 clock-latency-ns = <244144>; /* 8 32k periods */
20 #cooling-cells = <2>;
24 compatible = "arm,cortex-a53";
[all …]
/kernel/liteos_m/tools/
Dmem_analysis.py2 # -*- coding: utf-8 -*-
10 # http://www.apache.org/licenses/LICENSE-2.0
45 def storage_static_data(offset, section, sizeHex, symbol, lib, obj): argument
48 static_map[g_row_num] = {'offsets' : "offsets", 'section' : "section",\
54 static_map[g_row_num] = {'offsets': offset, 'section' : section,\
66 c.value = values.get('section')
77 wb.save('static_symbol-%s.xlsx' %datetime.datetime.now().strftime('%Y-%m-%d %H_%M_%S'))
87 target_list.append('{:<30s}'.format(values.get('section')))
155 wb.save('dync_mem-%s.xlsx' %datetime.datetime.now().strftime('%Y-%m-%d %H_%M_%S'))
209 elif line.startswith(' .sram.text.'):
[all …]
/kernel/linux/linux-4.19/Documentation/bus-devices/
Dti-gpmc.txt6 * Asynchronous SRAM like memories and application specific integrated
10 * Pseudo-SRAM devices
13 IP details: http://www.ti.com/lit/pdf/spruh73 section 7.1
68 4. read async non-muxed
80 6. read sync non-muxed
93 8. write async non-muxed
107 10. write sync non-muxed
/kernel/linux/linux-5.10/arch/arm/mach-rockchip/
Dsleep.S1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author: Tony Xie <tony.xie@rock-chips.com>
14 * ddr to sram for system resumeing.
15 * so it is ".data section".
64 .word . - rockchip_slp_cpu_resume
/kernel/linux/linux-5.10/arch/csky/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
119 In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not.
162 # VA_BITS - PAGE_SHIFT - 3
196 prompt "C-SKY PMU type"
226 bool "Tightly-Coupled/Sram Memory"
229 The implementation are not only used by TCM (Tightly-Coupled Meory)
230 but also used by sram on SOC bus. It follow existed linux tcm
232 re-used directly.
276 bool "Symmetric Multi-Processing (SMP) support for C-SKY"
281 int "Maximum number of CPUs (2-32)"
[all …]
/kernel/linux/linux-5.10/Documentation/driver-api/memory-devices/
Dti-gpmc.rst1 .. SPDX-License-Identifier: GPL-2.0
10 * Asynchronous SRAM like memories and application specific integrated
14 * Pseudo-SRAM devices
17 IP details: https://www.ti.com/lit/pdf/spruh73 section 7.1
85 4. read async non-muxed
107 6. read sync non-muxed
131 8. write async non-muxed
157 10. write sync non-muxed
/kernel/linux/linux-4.19/arch/arm/mach-rockchip/
Dsleep.S3 * Author: Tony Xie <tony.xie@rock-chips.com>
23 * ddr to sram for system resumeing.
24 * so it is ".data section".
73 .word . - rockchip_slp_cpu_resume

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