Home
last modified time | relevance | path

Searched +full:sun4i +full:- +full:a10 +full:- +full:apb1 +full:- +full:clk (Results 1 – 9 of 9) sorted by relevance

/kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/
Dsunxi.txt1 Device Tree Clock bindings for arch-sunxi
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
10 "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
13 "allwinner,sun4i-a10-pll3-clk" - for the video PLL clock on A10
14 "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
15 "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dallwinner,sun4i-a10-gates-clk.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-gates-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Bus Gates Clock Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
24 - const: allwinner,sun4i-a10-gates-clk
25 - const: allwinner,sun4i-a10-axi-gates-clk
[all …]
Dallwinner,sun4i-a10-apb1-clk.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-apb1-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 APB1 Bus Clock Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
20 const: allwinner,sun4i-a10-apb1-clk
30 clock-output-names:
[all …]
/kernel/linux/linux-5.10/drivers/clk/sunxi/
Dclk-simple-gates.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
43 number = of_property_count_u32_elems(node, "clock-indices"); in sunxi_simple_gates_setup()
44 of_property_read_u32_index(node, "clock-indices", number - 1, &number); in sunxi_simple_gates_setup()
46 clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL); in sunxi_simple_gates_setup()
47 if (!clk_data->clks) in sunxi_simple_gates_setup()
50 of_property_for_each_u32(node, "clock-indices", prop, p, index) { in sunxi_simple_gates_setup()
51 of_property_read_string_index(node, "clock-output-names", in sunxi_simple_gates_setup()
[all …]
Dclk-sunxi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
45 if (req->rate >= 768000000 || req->rate == 42000000 || in sun4i_get_pll1_factors()
[all …]
/kernel/linux/linux-4.19/drivers/clk/sunxi/
Dclk-simple-gates.c4 * Maxime Ripard <maxime.ripard@free-electrons.com>
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
51 number = of_property_count_u32_elems(node, "clock-indices"); in sunxi_simple_gates_setup()
52 of_property_read_u32_index(node, "clock-indices", number - 1, &number); in sunxi_simple_gates_setup()
54 clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL); in sunxi_simple_gates_setup()
55 if (!clk_data->clks) in sunxi_simple_gates_setup()
58 of_property_for_each_u32(node, "clock-indices", prop, p, index) { in sunxi_simple_gates_setup()
59 of_property_read_string_index(node, "clock-output-names", in sunxi_simple_gates_setup()
65 clk_data->clks[index] = clk_register_gate(NULL, clk_name, in sunxi_simple_gates_setup()
[all …]
Dclk-sunxi.c17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
22 #include <linux/reset-controller.h>
27 #include "clk-factors.h"
35 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
46 div = req->rate / 6000000; in sun4i_get_pll1_factors()
47 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
50 req->m = 0; in sun4i_get_pll1_factors()
53 if (req->rate >= 768000000 || req->rate == 42000000 || in sun4i_get_pll1_factors()
54 req->rate == 54000000) in sun4i_get_pll1_factors()
[all …]
/kernel/linux/linux-4.19/drivers/clk/sunxi-ng/
Dccu-sun4i-a10.c16 #include <linux/clk-provider.h>
33 #include "ccu-sun4i-a10.h"
43 .hw.init = CLK_HW_INIT("pll-core",
55 * With sigma-delta modulation for fractional-N on the audio PLL,
78 .hw.init = CLK_HW_INIT("pll-audio-base",
96 .hw.init = CLK_HW_INIT("pll-video0",
111 .hw.init = CLK_HW_INIT("pll-ve",
124 .hw.init = CLK_HW_INIT("pll-ve",
137 .hw.init = CLK_HW_INIT("pll-ddr-base",
144 static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,
[all …]
/kernel/linux/linux-5.10/drivers/clk/sunxi-ng/
Dccu-sun4i-a10.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
26 #include "ccu-sun4i-a10.h"
36 .hw.init = CLK_HW_INIT("pll-core",
48 * With sigma-delta modulation for fractional-N on the audio PLL,
71 .hw.init = CLK_HW_INIT("pll-audio-base",
89 .hw.init = CLK_HW_INIT("pll-video0",
104 .hw.init = CLK_HW_INIT("pll-ve",
117 .hw.init = CLK_HW_INIT("pll-ve",
130 .hw.init = CLK_HW_INIT("pll-ddr-base",
[all …]