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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/
Dallwinner,sun5i-a13-hstimer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/allwinner,sun5i-a13-hstimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A13 High-Speed Timer Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - const: allwinner,sun5i-a13-hstimer
17 - const: allwinner,sun7i-a20-hstimer
18 - items:
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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/timer/
Dallwinner,sun5i-a13-hstimer.txt5 - compatible : should be "allwinner,sun5i-a13-hstimer" or
6 "allwinner,sun7i-a20-hstimer"
7 - reg : Specifies base physical address and size of the registers.
8 - interrupts : The interrupts of these timers (2 for the sun5i IP, 4 for the sun7i
10 - clocks: phandle to the source clock (usually the AHB clock)
13 - resets: phandle to a reset controller asserting the timer
18 compatible = "allwinner,sun7i-a20-hstimer";
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dsun7i-a20.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
49 #include <dt-bindings/dma/sun4i-a10.h>
50 #include <dt-bindings/clock/sun7i-a20-ccu.h>
51 #include <dt-bindings/reset/sun4i-a10-ccu.h>
54 interrupt-parent = <&gic>;
61 #address-cells = <1>;
62 #size-cells = <1>;
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Dsun6i-a31.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
50 #include <dt-bindings/clock/sun6i-a31-ccu.h>
51 #include <dt-bindings/reset/sun6i-a31-ccu.h>
54 interrupt-parent = <&gic>;
61 #address-cells = <1>;
62 #size-cells = <1>;
66 compatible = "allwinner,simple-framebuffer",
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dsun7i-a20.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/dma/sun4i-a10.h>
48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
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Dsun6i-a31.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
49 #include <dt-bindings/reset/sun6i-a31-ccu.h>
52 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <1>;
61 #address-cells = <1>;
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/kernel/linux/linux-4.19/drivers/clocksource/
Dtimer-sun5i.c2 * Allwinner SoCs hstimer driver.
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
75 u32 old = readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1)); in sun5i_clkevt_sync()
77 while ((old - readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS) in sun5i_clkevt_sync()
83 u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
84 writel(val & ~TIMER_CTL_ENABLE, ce->timer.base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
91 writel(delay, ce->timer.base + TIMER_INTVAL_LO_REG(timer)); in sun5i_clkevt_time_setup()
96 u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_start()
104 ce->timer.base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_start()
129 sun5i_clkevt_time_setup(ce, 0, ce->timer.ticks_per_jiffy); in sun5i_clkevt_set_periodic()
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/kernel/linux/linux-5.10/drivers/clocksource/
Dtimer-sun5i.c2 * Allwinner SoCs hstimer driver.
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
75 u32 old = readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1)); in sun5i_clkevt_sync()
77 while ((old - readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS) in sun5i_clkevt_sync()
83 u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
84 writel(val & ~TIMER_CTL_ENABLE, ce->timer.base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
91 writel(delay, ce->timer.base + TIMER_INTVAL_LO_REG(timer)); in sun5i_clkevt_time_setup()
96 u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_start()
104 ce->timer.base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_start()
129 sun5i_clkevt_time_setup(ce, 0, ce->timer.ticks_per_jiffy); in sun5i_clkevt_set_periodic()
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/kernel/linux/linux-4.19/drivers/clk/sunxi-ng/
Dccu-sun4i-a10.c16 #include <linux/clk-provider.h>
33 #include "ccu-sun4i-a10.h"
43 .hw.init = CLK_HW_INIT("pll-core",
55 * With sigma-delta modulation for fractional-N on the audio PLL,
78 .hw.init = CLK_HW_INIT("pll-audio-base",
96 .hw.init = CLK_HW_INIT("pll-video0",
111 .hw.init = CLK_HW_INIT("pll-ve",
124 .hw.init = CLK_HW_INIT("pll-ve",
137 .hw.init = CLK_HW_INIT("pll-ddr-base",
144 static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,
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/kernel/linux/linux-5.10/drivers/clk/sunxi-ng/
Dccu-sun4i-a10.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
26 #include "ccu-sun4i-a10.h"
36 .hw.init = CLK_HW_INIT("pll-core",
48 * With sigma-delta modulation for fractional-N on the audio PLL,
71 .hw.init = CLK_HW_INIT("pll-audio-base",
89 .hw.init = CLK_HW_INIT("pll-video0",
104 .hw.init = CLK_HW_INIT("pll-ve",
117 .hw.init = CLK_HW_INIT("pll-ve",
130 .hw.init = CLK_HW_INIT("pll-ddr-base",
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