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Searched +full:sun9i +full:- +full:a80 +full:- +full:apb0 +full:- +full:clk (Results 1 – 11 of 11) sorted by relevance

/kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/
Dsunxi.txt1 Device Tree Clock bindings for arch-sunxi
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
10 "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
13 "allwinner,sun4i-a10-pll3-clk" - for the video PLL clock on A10
14 "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
15 "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dallwinner,sun9i-a80-apb0-clk.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-apb0-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A80 APB0 Bus Clock Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
21 - allwinner,sun9i-a80-apb0-clk
22 - allwinner,sun9i-a80-apb1-clk
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Dallwinner,sun4i-a10-gates-clk.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-gates-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
24 - const: allwinner,sun4i-a10-gates-clk
25 - const: allwinner,sun4i-a10-axi-gates-clk
26 - const: allwinner,sun4i-a10-ahb-gates-clk
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/kernel/linux/linux-5.10/drivers/clk/sunxi/
Dclk-simple-gates.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
43 number = of_property_count_u32_elems(node, "clock-indices"); in sunxi_simple_gates_setup()
44 of_property_read_u32_index(node, "clock-indices", number - 1, &number); in sunxi_simple_gates_setup()
46 clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL); in sunxi_simple_gates_setup()
47 if (!clk_data->clks) in sunxi_simple_gates_setup()
50 of_property_for_each_u32(node, "clock-indices", prop, p, index) { in sunxi_simple_gates_setup()
51 of_property_read_string_index(node, "clock-output-names", in sunxi_simple_gates_setup()
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Dclk-sun9i-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2014 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
14 #include "clk-factors.h"
18 * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
33 n = DIV_ROUND_UP(req->rate, 6000000); in sun9i_a80_get_pll4_factors()
53 req->rate = ((24000000 * n) >> p) / (m + 1); in sun9i_a80_get_pll4_factors()
54 req->n = n; in sun9i_a80_get_pll4_factors()
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/kernel/linux/linux-4.19/drivers/clk/sunxi/
Dclk-simple-gates.c4 * Maxime Ripard <maxime.ripard@free-electrons.com>
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
51 number = of_property_count_u32_elems(node, "clock-indices"); in sunxi_simple_gates_setup()
52 of_property_read_u32_index(node, "clock-indices", number - 1, &number); in sunxi_simple_gates_setup()
54 clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL); in sunxi_simple_gates_setup()
55 if (!clk_data->clks) in sunxi_simple_gates_setup()
58 of_property_for_each_u32(node, "clock-indices", prop, p, index) { in sunxi_simple_gates_setup()
59 of_property_read_string_index(node, "clock-output-names", in sunxi_simple_gates_setup()
65 clk_data->clks[index] = clk_register_gate(NULL, clk_name, in sunxi_simple_gates_setup()
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Dclk-sun9i-core.c2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
23 #include "clk-factors.h"
27 * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
42 n = DIV_ROUND_UP(req->rate, 6000000); in sun9i_a80_get_pll4_factors()
62 req->rate = ((24000000 * n) >> p) / (m + 1); in sun9i_a80_get_pll4_factors()
63 req->n = n; in sun9i_a80_get_pll4_factors()
64 req->m = m; in sun9i_a80_get_pll4_factors()
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/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dsun9i-a80.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dsun9i-a80.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
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/kernel/linux/linux-5.10/drivers/clk/sunxi-ng/
Dccu-sun9i-a80.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
21 #include "ccu-sun9i-a80.h"
28 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
43 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
57 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
79 .hw.init = CLK_HW_INIT("pll-audio", "osc24M",
95 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
111 .hw.init = CLK_HW_INIT("pll-ve", "osc24M",
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/kernel/linux/linux-4.19/drivers/clk/sunxi-ng/
Dccu-sun9i-a80.c2 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
14 #include <linux/clk-provider.h>
28 #include "ccu-sun9i-a80.h"
35 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
50 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
64 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
86 .hw.init = CLK_HW_INIT("pll-audio", "osc24M",
102 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
118 .hw.init = CLK_HW_INIT("pll-ve", "osc24M",
134 .hw.init = CLK_HW_INIT("pll-ddr", "osc24M",
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