Searched +full:system +full:- +full:cache +full:- +full:controller (Results 1 – 25 of 769) sorted by relevance
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/socionext/ |
| D | socionext,uniphier-system-cache.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/uniphier/ |
| D | cache-uniphier.txt | 1 UniPhier outer cache controller
3 UniPhier SoCs are integrated with a full-custom outer cache controller system.
4 All of them have a level 2 cache controller, and some have a level 3 cache
5 controller as well.
8 - compatible: should be "socionext,uniphier-system-cache"
9 - reg: offsets and lengths of the register sets for the device. It should
12 - cache-unified: specifies the cache is a unified cache.
13 - cache-size: specifies the size in bytes of the cache
14 - cache-sets: specifies the number of associativity sets of the cache
15 - cache-line-size: specifies the line size in bytes
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| /kernel/linux/linux-4.19/drivers/eisa/ |
| D | eisa.ids | 6 # Marc Zyngier <maz@wild-wind.fr.eu.org>
10 ABP0510 "Advansys ABP-510 ISA SCSI Host Adapter"
11 ABP0540 "Advansys ABP-540/542 ISA SCSI Host Adapter"
12 ABP7401 "AdvanSys ABP-740/742 EISA Single Channel SCSI Host Adapter"
13 ABP7501 "AdvanSys ABP-750/752 EISA Dual Channel SCSI Host Adapter"
14 ACC1200 "ACCTON EtherCombo-32 Ethernet Adapter"
15 ACC120A "ACCTON EtherCombo-32 Ethernet Adapter"
18 ACE1010 "ACME Super Fast System Board"
22 ACE4010 "ACME Tape Controller"
24 ACE6010 "ACME Disk Controller"
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| /kernel/linux/linux-5.10/drivers/eisa/ |
| D | eisa.ids | 6 # Marc Zyngier <maz@wild-wind.fr.eu.org>
10 ABP0510 "Advansys ABP-510 ISA SCSI Host Adapter"
11 ABP0540 "Advansys ABP-540/542 ISA SCSI Host Adapter"
12 ABP7401 "AdvanSys ABP-740/742 EISA Single Channel SCSI Host Adapter"
13 ABP7501 "AdvanSys ABP-750/752 EISA Dual Channel SCSI Host Adapter"
14 ACC1200 "ACCTON EtherCombo-32 Ethernet Adapter"
15 ACC120A "ACCTON EtherCombo-32 Ethernet Adapter"
18 ACE1010 "ACME Super Fast System Board"
22 ACE4010 "ACME Tape Controller"
24 ACE6010 "ACME Disk Controller"
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/nds32/ |
| D | atl2c.txt | 1 * Andestech L2 cache Controller
3 The level-2 cache controller plays an important role in reducing memory latency
5 Level-2 cache controller in general enhances overall system performance
6 signigicantly and the system power consumption might be reduced as well by
10 representation of an Andestech L2 cache controller.
13 - compatible:
17 - reg : Physical base address and size of cache controller's memory mapped
18 - cache-unified : Specifies the cache is a unified cache.
19 - cache-level : Should be set to 2 for a level 2 cache.
23 cache-controller@e0500000 {
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/nds32/ |
| D | atl2c.txt | 1 * Andestech L2 cache Controller
3 The level-2 cache controller plays an important role in reducing memory latency
5 Level-2 cache controller in general enhances overall system performance
6 signigicantly and the system power consumption might be reduced as well by
10 representation of an Andestech L2 cache controller.
13 - compatible:
17 - reg : Physical base address and size of cache controller's memory mapped
18 - cache-unified : Specifies the cache is a unified cache.
19 - cache-level : Should be set to 2 for a level 2 cache.
23 cache-controller@e0500000 {
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/ |
| D | l2c2x0.txt | 1 * ARM L2 Cache Controller
4 PL310 and variants) based level 2 cache controller. All these various implementations
5 of the L2 cache controller have compatible programming models (Note 1).
6 Some of the properties that are just prefixed "cache-*" are taken from section
10 The ARM L2 cache representation in the device tree should be done as follows:
14 - compatible : should be one of:
15 "arm,pl310-cache"
16 "arm,l220-cache"
17 "arm,l210-cache"
18 "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/power/ |
| D | renesas,rcar-sysc.txt | 1 DT bindings for the Renesas R-Car (RZ/G) System Controller
3 == System Controller Node ==
5 The R-Car (RZ/G) System Controller provides power management for the CPU cores
9 - compatible: Must contain exactly one of the following:
10 - "renesas,r8a7743-sysc" (RZ/G1M)
11 - "renesas,r8a7745-sysc" (RZ/G1E)
12 - "renesas,r8a77470-sysc" (RZ/G1C)
13 - "renesas,r8a7779-sysc" (R-Car H1)
14 - "renesas,r8a7790-sysc" (R-Car H2)
15 - "renesas,r8a7791-sysc" (R-Car M2-W)
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/riscv/ |
| D | cpus.txt | 2 RISC-V CPU Bindings
5 The device tree allows to describe the layout of CPUs in a system through
13 with updates for 32-bit and 64-bit RISC-V systems provided in this document.
19 This document uses some terminology common to the RISC-V community that is not
23 the RISC-V ISA: a PC and some registers. This terminology is designed to
27 threads. Therefore this system has four harts.
33 The RISC-V architecture, in accordance with the Devicetree Specification,
37 - cpus node
45 - #address-cells
49 - #size-cells
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | l2c2x0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM L2 Cache Controller
10 - Rob Herring <robh@kernel.org>
14 PL220/PL310 and variants) based level 2 cache controller. All these various
15 implementations of the L2 cache controller have compatible programming
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/ |
| D | renesas,rcar-sysc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/power/renesas,rcar-sysc.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Renesas R-Car and RZ/G System Controller
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Magnus Damm <magnus.damm@gmail.com>
14 The R-Car (RZ/G) System Controller provides power management for the CPU
20 - renesas,r8a7742-sysc # RZ/G1H
21 - renesas,r8a7743-sysc # RZ/G1M
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| /kernel/linux/linux-5.10/arch/arm/mm/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
18 which has no memory control unit and cache.
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
69 A 32-bit RISC microprocessor based on the ARM9 processor core
70 which has no memory control unit and cache.
147 instruction sequences for cache and TLB operations. Curiously,
166 Branch Target Buffer, Unified TLB and cache line size 16.
182 ARM940T is a member of the ARM9TDMI family of general-
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| /kernel/linux/linux-4.19/arch/arm/mm/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
18 which has no memory control unit and cache.
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
69 A 32-bit RISC microprocessor based on the ARM9 processor core
70 which has no memory control unit and cache.
147 instruction sequences for cache and TLB operations. Curiously,
166 Branch Target Buffer, Unified TLB and cache line size 16.
182 ARM940T is a member of the ARM9TDMI family of general-
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| /kernel/linux/linux-4.19/Documentation/cgroup-v1/ |
| D | memory.txt | 1 Memory Resource Controller
8 NOTE: The Memory Resource Controller has generically been referred to as the
9 memory controller in this document. Do not confuse memory controller
10 used here with the memory controller that is used in hardware.
14 When we mention a cgroup (cgroupfs's directory) with memory controller,
15 we call it "memory cgroup". When you see git-log and source code, you'll
19 Benefits and Purpose of the memory controller
21 The memory controller isolates the memory behaviour of a group of tasks
22 from the rest of the system. The article on LWN [12] mentions some probable
23 uses of the memory controller. The memory controller can be used to
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| /kernel/linux/linux-5.10/Documentation/admin-guide/cgroup-v1/ |
| D | memory.rst | 2 Memory Resource Controller
12 The Memory Resource Controller has generically been referred to as the
13 memory controller in this document. Do not confuse memory controller
14 used here with the memory controller that is used in hardware.
17 When we mention a cgroup (cgroupfs's directory) with memory controller,
18 we call it "memory cgroup". When you see git-log and source code, you'll
22 Benefits and Purpose of the memory controller
25 The memory controller isolates the memory behaviour of a group of tasks
26 from the rest of the system. The article on LWN [12] mentions some probable
27 uses of the memory controller. The memory controller can be used to
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| /kernel/linux/linux-5.10/drivers/edac/ |
| D | Kconfig | 16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
59 Not all machines support hardware-driven error report. Some of those
60 provide a BIOS-driven error report mechanism via ACPI, using the
64 When this option is enabled, it will disable the hardware-driven
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | baikal,bt1-l2-ctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 L2-cache Control Block
11 - Serge Semin <fancer.lancer@gmail.com>
14 By means of the System Controller Baikal-T1 SoC exposes a few settings to
15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
16 to change the Tag, Data and Way-select RAM access latencies. Baikal-T1
17 L2-cache controller block is responsible for the tuning. Its DT node is
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,llcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Last Level Cache Controller
10 - Rishabh Bhatnagar <rishabhb@codeaurora.org>
11 - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
14 LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
17 common pool of memory. Cache memory is divided into partitions called slices
24 - qcom,sc7180-llcc
25 - qcom,sdm845-llcc
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| /kernel/linux/linux-4.19/Documentation/arm64/ |
| D | booting.txt | 11 (EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
12 counterpart. EL2 is the hypervisor level and exists only in non-secure
31 ---------------------------
36 kernel will use for volatile data storage in the system. It performs
44 -------------------------
48 The device tree blob (dtb) must be placed on an 8-byte boundary and must
57 ------------------------------
69 ------------------------
73 The decompressed kernel image contains a 64-byte header as follows:
89 - As of v3.17, all fields are little endian unless stated otherwise.
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| /kernel/linux/linux-4.19/init/ |
| D | Kconfig | 5 default "/lib/modules/$(shell,uname -r)/.config"
6 default "/etc/kernel-config"
7 default "/boot/config-$(shell,uname -r)"
12 def_bool $(success,$(CC) --version | head -n 1 | grep -q gcc)
16 default $(shell,$(srctree)/scripts/gcc-version.sh -p $(CC) | sed 's/^0*//') if CC_IS_GCC
20 def_bool $(success,$(CC) --version | head -n 1 | grep -q clang)
24 default $(shell,$(srctree)/scripts/clang-version.sh $(CC))
27 def_bool $(success,$(srctree)/scripts/gcc-goto.sh $(CC))
76 drivers to compile-test them.
83 string "Local version - append to kernel release"
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | uniphier-pro5.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
9 compatible = "socionext,uniphier-pro5";
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
22 enable-method = "psci";
23 next-level-cache = <&l2>;
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| /kernel/linux/linux-5.10/drivers/memory/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
7 bool "Memory Controller drivers"
9 This option allows to enable specific memory controller drivers,
29 This selects the ARM PrimeCell PL172 MultiPort Memory Controller.
30 If you have an embedded system with an AMBA bus and a PL172
31 controller, say Y or M here.
34 bool "Atmel (Multi-port DDR-)SDRAM Controller"
39 This driver is for Atmel SDRAM Controller or Atmel Multi-port
40 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
41 Starting with the at91sam9g45, this controller supports SDR, DDR and
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| /kernel/linux/linux-5.10/init/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 default "/lib/modules/$(shell,uname -r)/.config"
7 default "/etc/kernel-config"
8 default "/boot/config-$(shell,uname -r)"
17 - Re-run Kconfig when the compiler is updated
22 - Ensure full rebuild when the compier is updated
24 fixdep adds include/config/cc/version/text.h into the auto-generated
29 def_bool $(success,echo "$(CC_VERSION_TEXT)" | grep -q gcc)
33 default $(shell,$(srctree)/scripts/gcc-version.sh $(CC)) if CC_IS_GCC
38 default $(shell,$(LD) --version | $(srctree)/scripts/ld-version.sh)
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | armada-xp-98dx3236.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 #include "armada-370-xp.dtsi"
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,98dx3236-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
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| /kernel/linux/linux-4.19/Documentation/blockdev/ |
| D | README.DAC960 | 14 Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
33 and DAC960PJ/PG/PU/PD/PL. See below for a complete controller list as well as
40 by the driver at startup, along with any subsequent system messages relevant to
41 the controller's operation, and a detailed description of your system's
47 Please consult the RAID controller documentation for detailed information
64 of the controller and adding new disk drives, most everything can be handled
65 from Linux while the system is operational.
67 The DAC960 driver is architected to support up to 8 controllers per system.
68 Each DAC960 parallel SCSI controller can support up to 15 disk drives per
69 channel, for a maximum of 60 drives on a four channel controller; the fibre
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