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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra20-pmc
18 - nvidia,tegra30-pmc
[all …]
Dnvidia,tegra186-pmc.txt1 NVIDIA Tegra Power Management Controller (PMC)
4 - compatible: Should contain one of the following:
5 - "nvidia,tegra186-pmc": for Tegra186
6 - "nvidia,tegra194-pmc": for Tegra194
7 - "nvidia,tegra234-pmc": for Tegra234
8 - reg: Must contain an (offset, length) pair of the register set for each
9 entry in reg-names.
10 - reg-names: Must include the following entries:
11 - "pmc"
12 - "wake"
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-pmc.txt1 NVIDIA Tegra Power Management Controller (PMC)
5 The PMC block interacts with an external Power Management Unit. The PMC
7 modes. It provides power-gating controllers for SoC and CPU power-islands.
10 - name : Should be pmc
11 - compatible : Should contain one of the following:
12 For Tegra20 must contain "nvidia,tegra20-pmc".
13 For Tegra30 must contain "nvidia,tegra30-pmc".
14 For Tegra114 must contain "nvidia,tegra114-pmc"
15 For Tegra124 must contain "nvidia,tegra124-pmc"
16 For Tegra132 must contain "nvidia,tegra124-pmc"
[all …]
Dnvidia,tegra186-pmc.txt1 NVIDIA Tegra Power Management Controller (PMC)
4 - compatible: Should contain one of the following:
5 - "nvidia,tegra186-pmc": for Tegra186
6 - "nvidia,tegra194-pmc": for Tegra194
7 - reg: Must contain an (offset, length) pair of the register set for each
8 entry in reg-names.
9 - reg-names: Must include the following entries:
10 - "pmc"
11 - "wake"
12 - "aotag"
[all …]
/kernel/linux/linux-4.19/drivers/soc/tegra/
Dpmc.c2 * drivers/soc/tegra/pmc.c
20 #define pr_fmt(fmt) "tegra-pmc: " fmt
24 #include <linux/clk/tegra.h>
44 #include <soc/tegra/common.h>
45 #include <soc/tegra/fuse.h>
46 #include <soc/tegra/pmc.h>
129 struct tegra_pmc *pmc; member
165 void (*init)(struct tegra_pmc *pmc);
166 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
172 * struct tegra_pmc - NVIDIA Tegra PMC
[all …]
/kernel/linux/linux-5.10/drivers/soc/tegra/
Dpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/soc/tegra/pmc.c
6 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
19 #include <linux/clk/tegra.h>
36 #include <linux/pinctrl/pinconf-generic.h>
47 #include <soc/tegra/common.h>
[all …]
/kernel/linux/linux-4.19/drivers/clk/tegra/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += clk.o
3 obj-y += clk-audio-sync.o
4 obj-y += clk-dfll.o
5 obj-y += clk-divider.o
6 obj-y += clk-periph.o
7 obj-y += clk-periph-fixed.o
8 obj-y += clk-periph-gate.o
9 obj-y += clk-pll.o
10 obj-y += clk-pll-out.o
[all …]
Dclk.h20 #include <linux/clk-provider.h>
25 * struct tegra_clk_sync_source - external clock source from codec
27 * @hw: handle between common and hardware-specific interfaces
47 * struct tegra_clk_frac_div - fractional divider clock
49 * @hw: handle between common and hardware-specific interfaces
51 * @flags: hardware-specific flags
58 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
59 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
61 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when
64 * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-tegra/
Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-tegra/platsmp.c
12 #include <linux/clk/tegra.h>
21 #include <soc/tegra/flowctrl.h>
22 #include <soc/tegra/fuse.h>
23 #include <soc/tegra/pmc.h>
26 #include <asm/mach-types.h>
50 * power-gated via the flow controller). This will have no in tegra20_boot_secondary()
58 * power-gate the CPU this will cause the flow controller to in tegra20_boot_secondary()
84 * power will be resumed automatically after un-halting the in tegra30_boot_secondary()
[all …]
Dtegra.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * NVIDIA Tegra SoC device tree board support
11 #include <linux/clk/tegra.h>
12 #include <linux/dma-mapping.h>
31 #include <soc/tegra/fuse.h>
32 #include <soc/tegra/pmc.h>
35 #include <asm/hardware/cache-l2x0.h>
38 #include <asm/mach-types.h>
50 * Storage for debug-macro.S's state.
53 * kernel is loaded. The data is declared here rather than debug-macro.S so
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-tegra/
Dplatsmp.c2 * linux/arch/arm/mach-tegra/platsmp.c
15 #include <linux/clk/tegra.h>
24 #include <soc/tegra/flowctrl.h>
25 #include <soc/tegra/fuse.h>
26 #include <soc/tegra/pmc.h>
29 #include <asm/mach-types.h>
53 * power-gated via the flow controller). This will have no in tegra20_boot_secondary()
61 * power-gate the CPU this will cause the flow controller to in tegra20_boot_secondary()
87 * power will be resumed automatically after un-halting the in tegra30_boot_secondary()
108 * be un-gated by un-toggling the power gate register in tegra30_boot_secondary()
[all …]
Dtegra.c2 * NVIDIA Tegra SoC device tree board support
20 #include <linux/clk/tegra.h>
21 #include <linux/dma-mapping.h>
38 #include <soc/tegra/fuse.h>
39 #include <soc/tegra/pmc.h>
41 #include <asm/hardware/cache-l2x0.h>
44 #include <asm/mach-types.h>
58 * Storage for debug-macro.S's state.
61 * kernel is loaded. The data is declared here rather than debug-macro.S so
62 * that multiple inclusions of debug-macro.S point at the same data.
[all …]
Dpm.c2 * CPU complex suspend & resume functions for Tegra SoCs
4 * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
19 #include <linux/clk/tegra.h>
30 #include <soc/tegra/flowctrl.h>
31 #include <soc/tegra/fuse.h>
32 #include <soc/tegra/pm.h>
33 #include <soc/tegra/pmc.h>
37 #include <asm/proc-fns.h>
198 cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); in tegra_idle_lp2_last()
208 * The Tegra devices support suspending to LP1 or lower currently. in tegra_pm_validate_suspend_mode()
[all …]
/kernel/linux/linux-5.10/drivers/cpuidle/
Dcpuidle-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * CPU idle driver for Tegra CPUs
5 * Copyright (c) 2010-2013, NVIDIA Corporation.
15 #define pr_fmt(fmt) "tegra-cpuidle: " fmt
26 #include <linux/clk/tegra.h>
29 #include <soc/tegra/cpuidle.h>
30 #include <soc/tegra/flowctrl.h>
31 #include <soc/tegra/fuse.h>
32 #include <soc/tegra/irq.h>
33 #include <soc/tegra/pm.h>
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/nouveau/include/nvif/
Dos.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #include <linux/i2c-algo-bit.h>
17 #include <linux/io-mapping.h>
35 #include <soc/tegra/fuse.h>
36 #include <soc/tegra/pmc.h>
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/include/nvif/
Dos.h1 /* SPDX-License-Identifier: MIT */
15 #include <linux/i2c-algo-bit.h>
17 #include <linux/io-mapping.h>
35 #include <soc/tegra/fuse.h>
36 #include <soc/tegra/pmc.h>
/kernel/linux/linux-5.10/drivers/clk/tegra/
Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
59 * Tegra CLK_OUT_ENB registers have some undefined bits which are not used and
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtegra20-paz00.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
6 #include "tegra20-cpu-opp.dtsi"
7 #include "tegra20-cpu-opp-microvolt.dtsi"
21 stdout-path = "serial0:115200n8";
40 vdd-supply = <&hdmi_vdd_reg>;
41 pll-supply = <&hdmi_pll_reg>;
43 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
44 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
[all …]
Dtegra20-tamonten.dtsi1 // SPDX-License-Identifier: GPL-2.0
15 stdout-path = "serial0:115200n8";
24 vdd-supply = <&hdmi_vdd_reg>;
25 pll-supply = <&hdmi_pll_reg>;
27 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
28 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
34 pinctrl-names = "default";
35 pinctrl-0 = <&state_default>;
144 pmc {
145 nvidia,pins = "pmc";
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dnvidia,tegra20-pinmux.txt4 - compatible: "nvidia,tegra20-pinmux"
5 - reg: Should contain the register physical address and length for each of
6 the tri-state, mux, pull-up/down, and pad control register sets.
8 Please refer to pinctrl-bindings.txt in this directory for details of the
12 Tegra's pin configuration nodes act as a container for an arbitrary number of
16 parameters, such as pull-up, tristate, drive strength, etc.
30 Required subnode-properties:
31 - nvidia,pins : An array of strings. Each string contains the name of a pin or
34 Optional subnode-properties:
35 - nvidia,function: A string containing the name of the function to mux to the
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/pinctrl/
Dnvidia,tegra20-pinmux.txt4 - compatible: "nvidia,tegra20-pinmux"
5 - reg: Should contain the register physical address and length for each of
6 the tri-state, mux, pull-up/down, and pad control register sets.
8 Please refer to pinctrl-bindings.txt in this directory for details of the
12 Tegra's pin configuration nodes act as a container for an arbitrary number of
16 parameters, such as pull-up, tristate, drive strength, etc.
30 Required subnode-properties:
31 - nvidia,pins : An array of strings. Each string contains the name of a pin or
34 Optional subnode-properties:
35 - nvidia,function: A string containing the name of the function to mux to the
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/tegra/
Dvic.c20 #include <soc/tegra/pmc.h>
53 writel(value, vic->regs + offset); in vic_writel()
60 return clk_prepare_enable(vic->clk); in vic_runtime_resume()
67 clk_disable_unprepare(vic->clk); in vic_runtime_suspend()
69 vic->booted = false; in vic_runtime_suspend()
80 if (vic->booted) in vic_boot()
89 err = falcon_boot(&vic->falcon); in vic_boot()
93 hdr = vic->falcon.firmware.vaddr; in vic_boot()
95 hdr = vic->falcon.firmware.vaddr + in vic_boot()
99 falcon_execute_method(&vic->falcon, VIC_SET_APPLICATION_ID, 1); in vic_boot()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/
Dnvidia,tegra124-xusb.txt1 NVIDIA Tegra xHCI controller
4 The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed by
5 the Tegra XUSB pad controller.
8 --------------------
9 - compatible: Must be:
10 - Tegra124: "nvidia,tegra124-xusb"
11 - Tegra132: "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"
12 - Tegra210: "nvidia,tegra210-xusb"
13 - Tegra186: "nvidia,tegra186-xusb"
14 - reg: Must contain the base and length of the xHCI host registers, XUSB FPCI
[all …]
/kernel/linux/linux-5.10/drivers/ata/
Dahci_tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <soc/tegra/fuse.h>
21 #include <soc/tegra/pmc.h>
25 #define DRV_NAME "tegra-ahci"
179 struct tegra_ahci_priv *tegra = hpriv->plat_data; in tegra_ahci_handle_quirks() local
182 if (tegra->sata_aux_regs && !tegra->soc->supports_devslp) { in tegra_ahci_handle_quirks()
183 val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); in tegra_ahci_handle_quirks()
185 writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); in tegra_ahci_handle_quirks()
191 struct tegra_ahci_priv *tegra = hpriv->plat_data; in tegra124_ahci_init() local
203 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); in tegra124_ahci_init()
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dtegra20-tamonten.dtsi1 // SPDX-License-Identifier: GPL-2.0
15 stdout-path = "serial0:115200n8";
24 vdd-supply = <&hdmi_vdd_reg>;
25 pll-supply = <&hdmi_pll_reg>;
27 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
28 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
34 pinctrl-names = "default";
35 pinctrl-0 = <&state_default>;
144 pmc {
145 nvidia,pins = "pmc";
[all …]

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