| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | nvidia,tegra124-car.txt | 1 NVIDIA Tegra124 and Tegra132 Clock And Reset Controller
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
11 - reg : Should contain CAR registers location and length
12 - clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14 - #clock-cells : Should be 1.
17 <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
18 to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
19 (for Tegra124-specific clocks).
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/ |
| D | nvidia,tegra124-car.txt | 1 NVIDIA Tegra124 and Tegra132 Clock And Reset Controller
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
11 - reg : Should contain CAR registers location and length
12 - clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14 - #clock-cells : Should be 1.
17 <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
18 to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
19 (for Tegra124-specific clocks).
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| /kernel/linux/linux-5.10/drivers/memory/tegra/ |
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 tegra-mc-y := mc.o
4 tegra-mc-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20.o
5 tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o
6 tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
7 tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
8 tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
9 tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
11 obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
13 obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
15 This driver is for the External Memory Controller (EMC) found on
16 Tegra20 chips. The EMC controls the external DRAM on the board.
25 This driver is for the External Memory Controller (EMC) found on
26 Tegra30 chips. The EMC controls the external DRAM on the board.
31 bool "NVIDIA Tegra124 External Memory Controller driver"
35 This driver is for the External Memory Controller (EMC) found on
36 Tegra124 chips. The EMC controls the external DRAM on the board.
49 This driver is for the External Memory Controller (EMC) found on
50 Tegra210 chips. The EMC controls the external DRAM on the board.
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| D | tegra124-emc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
21 #include <soc/tegra/emc.h>
488 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument
491 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
492 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
495 static void emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
500 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
503 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()
509 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
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| D | tegra30-emc.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
357 static int emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
362 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
364 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()
368 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
377 struct tegra_emc *emc = data; in tegra_emc_isr() local
381 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
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| /kernel/linux/linux-5.10/drivers/clk/tegra/ |
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += clk.o
3 obj-y += clk-audio-sync.o
4 obj-y += clk-dfll.o
5 obj-y += clk-divider.o
6 obj-y += clk-periph.o
7 obj-y += clk-periph-fixed.o
8 obj-y += clk-periph-gate.o
9 obj-y += clk-pll.o
10 obj-y += clk-pll-out.o
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra124-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra124 SoC External Memory Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
26 - description: external memory clock
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| D | nvidia,tegra124-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra124 SoC Memory Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
16 two memory channels. The Tegra124 Memory Controller handles memory requests
22 const: nvidia,tegra124-mc
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra30-mc.txt | 4 memory-controller node
5 ----------------------
8 - compatible: Should be "nvidia,tegra<chip>-mc"
9 - reg: Physical base address and length of the controller's registers.
10 - clocks: Must contain an entry for each entry in clock-names.
11 See ../clocks/clock-bindings.txt for details.
12 - clock-names: Must include the following entries:
13 - mc: the module's clock input
14 - interrupts: The interrupt outputs from the controller.
15 - #reset-cells : Should be 1. This cell represents memory client module ID.
[all …]
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| D | nvidia,tegra124-emc.txt | 1 NVIDIA Tegra124 SoC EMC (external memory controller)
5 - compatible : Should be "nvidia,tegra124-emc".
6 - reg : physical base address and length of the controller's registers.
7 - nvidia,memory-controller : phandle of the MC driver.
9 The node should contain a "emc-timings" subnode for each supported RAM type
13 Required properties for "emc-timings" nodes :
14 - nvidia,ram-code : Should contain the value of RAM_CODE this timing set is
17 Each "emc-timings" node should contain a "timing" subnode for every supported
18 EMC clock rate. The "timing" subnodes should have the clock rate in Hz as
22 - clock-frequency : Should contain the memory clock rate in Hz.
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| /kernel/linux/linux-4.19/drivers/memory/tegra/ |
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 tegra-mc-y := mc.o
4 tegra-mc-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20.o
5 tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o
6 tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
7 tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
8 tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
9 tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
11 obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
13 obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
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| D | tegra124-emc.c | 18 #include <linux/clk-provider.h>
29 #include <soc/tegra/emc.h>
488 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument
491 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
492 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
495 static void emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
500 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
503 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()
509 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
512 static void emc_seq_disable_auto_cal(struct tegra_emc *emc) in emc_seq_disable_auto_cal() argument
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| /kernel/linux/linux-4.19/arch/arm64/boot/dts/nvidia/ |
| D | tegra132.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
11 compatible = "nvidia,tegra132", "nvidia,tegra124";
12 interrupt-parent = <&lic>;
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| /kernel/linux/linux-4.19/drivers/clk/tegra/ |
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += clk.o
3 obj-y += clk-audio-sync.o
4 obj-y += clk-dfll.o
5 obj-y += clk-divider.o
6 obj-y += clk-periph.o
7 obj-y += clk-periph-fixed.o
8 obj-y += clk-periph-gate.o
9 obj-y += clk-pll.o
10 obj-y += clk-pll-out.o
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | tegra124.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
12 compatible = "nvidia,tegra124";
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | tegra124.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
11 compatible = "nvidia,tegra124";
12 interrupt-parent = <&lic>;
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra30-actmon.txt | 9 - compatible: should be "nvidia,tegra<chip>-actmon"
10 - reg: offset and length of the register set for the device
11 - interrupts: standard interrupt property
12 - clocks: Must contain a phandle and clock specifier pair for each entry in
13 clock-names. See ../../clock/clock-bindings.txt for details.
14 - clock-names: Must include the following entries:
15 - actmon
16 - emc
17 - resets: Must contain an entry for each entry in reset-names. See
19 - reset-names: Must include the following entries:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra30-actmon.txt | 9 - compatible: should be "nvidia,tegra<chip>-actmon"
10 - reg: offset and length of the register set for the device
11 - interrupts: standard interrupt property
12 - clocks: Must contain a phandle and clock specifier pair for each entry in
13 clock-names. See ../../clock/clock-bindings.txt for details.
14 - clock-names: Must include the following entries:
15 - actmon
16 - emc
17 - resets: Must contain an entry for each entry in reset-names. See
19 - reset-names: Must include the following entries:
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/nvidia/ |
| D | tegra132.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
12 compatible = "nvidia,tegra132", "nvidia,tegra124";
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| D | tegra210.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
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| /kernel/linux/linux-5.10/arch/arm/mach-tegra/ |
| D | sleep-tegra30.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <asm/asm-offsets.h>
143 * Puts the current CPU in wait-for-event mode on the flow controller
144 * and powergates it -- flags (in R0) indicate the request type.
147 * corrupts r0-r4, r10-r12
244 * CPU power-gating process, to avoid loading from SDRAM which
245 * are not supported once SDRAM is put into self-refresh.
247 * disabled before putting SDRAM into self-refresh to avoid
307 * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
376 * enabled by the Tegra30 CLK driver on an as-needed basis, see
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| /kernel/linux/linux-4.19/arch/arm/mach-tegra/ |
| D | sleep-tegra30.S | 22 #include <asm/asm-offsets.h>
152 * Puts the current CPU in wait-for-event mode on the flow controller
153 * and powergates it -- flags (in R0) indicate the request type.
156 * corrupts r0-r4, r10-r12
253 * CPU power-gating process, to avoid loading from SDRAM which
254 * are not supported once SDRAM is put into self-refresh.
256 * disabled before putting SDRAM into self-refresh to avoid
316 * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
421 movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base
426 cmp r10, #TEGRA124
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| /kernel/linux/linux-4.19/drivers/devfreq/ |
| D | tegra-devfreq.c | 68 * transaction takes 4 EMC clocks for Tegra124; So the COUNT_WEIGHT is
89 * struct tegra_devfreq_device_config - configuration specific to an ACTMON
108 * to be taken into account. This is to avoid increasing the EMC
142 * struct tegra_devfreq_device - state specific to an ACTMON device
196 return readl(tegra->regs + offset); in actmon_readl()
201 writel(val, tegra->regs + offset); in actmon_writel()
206 return readl(dev->regs + offset); in device_readl()
212 writel(val, dev->regs + offset); in device_writel()
223 u32 avg = dev->avg_count; in tegra_devfreq_update_avg_wmark()
224 u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ; in tegra_devfreq_update_avg_wmark()
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| /kernel/linux/linux-5.10/drivers/devfreq/ |
| D | tegra30-devfreq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
60 * transaction takes 4 EMC clocks for Tegra124; So the COUNT_WEIGHT is
81 * struct tegra_devfreq_device_config - configuration specific to an ACTMON
101 * increasing the EMC frequency when the CPU is very busy but not
135 * struct tegra_devfreq_device - state specific to an ACTMON device
195 return readl_relaxed(tegra->regs + offset); in actmon_readl()
200 writel_relaxed(val, tegra->regs + offset); in actmon_writel()
205 return readl_relaxed(dev->regs + offset); in device_readl()
211 writel_relaxed(val, dev->regs + offset); in device_writel()
229 u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ; in tegra_devfreq_update_avg_wmark()
[all …]
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