| /kernel/linux/linux-4.19/drivers/memory/tegra/ |
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 tegra-mc-y := mc.o
4 tegra-mc-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20.o
5 tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o
6 tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
7 tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
8 tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
9 tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
11 obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
13 obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
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| D | mc.c | 21 #include "mc.h"
54 { .compatible = "nvidia,tegra20-mc", .data = &tegra20_mc_soc },
57 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
60 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
63 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
66 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
69 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
75 static int terga_mc_block_dma_common(struct tegra_mc *mc, in terga_mc_block_dma_common() argument
81 spin_lock_irqsave(&mc->lock, flags); in terga_mc_block_dma_common()
83 value = mc_readl(mc, rst->control) | BIT(rst->bit); in terga_mc_block_dma_common()
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| D | tegra124-emc.c | 18 #include <linux/clk-provider.h>
31 #include <soc/tegra/mc.h>
474 struct tegra_mc *mc; member
491 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
492 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
500 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
503 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()
509 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
517 writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_seq_disable_auto_cal()
520 value = readl(emc->regs + EMC_AUTO_CAL_STATUS); in emc_seq_disable_auto_cal()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra124-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra124 SoC Memory Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
16 two memory channels. The Tegra124 Memory Controller handles memory requests
22 const: nvidia,tegra124-mc
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| D | nvidia,tegra124-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra124 SoC External Memory Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
26 - description: external memory clock
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| /kernel/linux/linux-5.10/drivers/memory/tegra/ |
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 tegra-mc-y := mc.o
4 tegra-mc-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20.o
5 tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o
6 tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
7 tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
8 tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
9 tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
11 obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
13 obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
7 This driver supports the Memory Controller (MC) hardware found on
31 bool "NVIDIA Tegra124 External Memory Controller driver"
36 Tegra124 chips. The EMC controls the external DRAM on the board.
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| D | mc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
20 #include "mc.h"
24 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
27 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
30 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
33 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
36 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
39 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
45 static int tegra_mc_block_dma_common(struct tegra_mc *mc, in tegra_mc_block_dma_common() argument
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| D | tegra30-emc.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
29 #include "mc.h"
328 struct tegra_mc *mc; member
362 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
364 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()
368 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
381 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
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| D | tegra124-emc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
23 #include <soc/tegra/mc.h>
466 struct tegra_mc *mc; member
491 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
492 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
500 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
503 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()
509 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
517 writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_seq_disable_auto_cal()
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| D | tegra124.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/memory/tegra124-mc.h>
11 #include "mc.h"
721 /* read-only */
736 /* read-only */
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra30-mc.txt | 4 memory-controller node
5 ----------------------
8 - compatible: Should be "nvidia,tegra<chip>-mc"
9 - reg: Physical base address and length of the controller's registers.
10 - clocks: Must contain an entry for each entry in clock-names.
11 See ../clocks/clock-bindings.txt for details.
12 - clock-names: Must include the following entries:
13 - mc: the module's clock input
14 - interrupts: The interrupt outputs from the controller.
15 - #reset-cells : Should be 1. This cell represents memory client module ID.
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| D | nvidia,tegra124-emc.txt | 1 NVIDIA Tegra124 SoC EMC (external memory controller)
5 - compatible : Should be "nvidia,tegra124-emc".
6 - reg : physical base address and length of the controller's registers.
7 - nvidia,memory-controller : phandle of the MC driver.
9 The node should contain a "emc-timings" subnode for each supported RAM type
13 Required properties for "emc-timings" nodes :
14 - nvidia,ram-code : Should contain the value of RAM_CODE this timing set is
17 Each "emc-timings" node should contain a "timing" subnode for every supported
22 - clock-frequency : Should contain the memory clock rate in Hz.
23 - The following properties contain EMC timing characterization values
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | tegra124.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
12 compatible = "nvidia,tegra124";
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | tegra124.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
11 compatible = "nvidia,tegra124";
12 interrupt-parent = <&lic>;
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| /kernel/linux/linux-4.19/arch/arm64/boot/dts/nvidia/ |
| D | tegra132.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
11 compatible = "nvidia,tegra132", "nvidia,tegra124";
12 interrupt-parent = <&lic>;
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| D | tegra210.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/thermal/tegra124-soctherm.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/nvidia/ |
| D | tegra132.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
12 compatible = "nvidia,tegra132", "nvidia,tegra124";
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| D | tegra210.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/ |
| D | nvidia,tegra-vde.txt | 4 - compatible : Must contain one of the following values:
5 - "nvidia,tegra20-vde"
6 - "nvidia,tegra30-vde"
7 - "nvidia,tegra114-vde"
8 - "nvidia,tegra124-vde"
9 - "nvidia,tegra132-vde"
10 - reg : Must contain an entry for each entry in reg-names.
11 - reg-names : Must include the following entries:
12 - sxe
13 - bsev
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/media/ |
| D | nvidia,tegra-vde.txt | 4 - compatible : Must contain one of the following values:
5 - "nvidia,tegra20-vde"
6 - "nvidia,tegra30-vde"
7 - "nvidia,tegra114-vde"
8 - "nvidia,tegra124-vde"
9 - "nvidia,tegra132-vde"
10 - reg : Must contain an entry for each entry in reg-names.
11 - reg-names : Must include the following entries:
12 - sxe
13 - bsev
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| /kernel/linux/linux-5.10/drivers/clk/tegra/ |
| D | clk-tegra124.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
7 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/tegra124-car.h>
15 #include <dt-bindings/reset/tegra124-car.h>
18 #include "clk-id.h"
22 * banks present in the Tegra124/132 CAR IP block. The banks are
95 #define MASK(x) (BIT(x) - 1)
995 { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC },
1053 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, in tegra124_periph_clk_init()
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| /kernel/linux/linux-4.19/drivers/clk/tegra/ |
| D | clk-tegra124.c | 2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
18 #include <linux/clk-provider.h>
25 #include <dt-bindings/clock/tegra124-car.h>
26 #include <dt-bindings/reset/tegra124-car.h>
29 #include "clk-id.h"
33 * banks present in the Tegra124/132 CAR IP block. The banks are
995 { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC },
1032 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, in tegra124_periph_clk_init()
1199 /* Tegra124 CPU clock and reset control functions */
1251 { .compatible = "nvidia,tegra124-pmc" },
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| /kernel/linux/linux-4.19/drivers/thermal/tegra/ |
| D | soctherm.c | 31 #include <dt-bindings/thermal/tegra124-soctherm.h>
155 #define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
158 (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
161 #define THROT_DEPTH_DIVIDEND(depth) ((256 * (100 - (depth)) / 100) - 1)
187 static const int min_low_temp = -127000;
244 * ccroc_writel() - writes a value to a CCROC register
253 writel(value, (ts->ccroc_regs + reg)); in ccroc_writel()
257 * ccroc_readl() - reads specified register from CCROC IP block
265 return readl(ts->ccroc_regs + reg); in ccroc_readl()
270 const struct tegra_tsensor *sensor = &tegra->soc->tsensors[i]; in enable_tsensor()
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| /kernel/linux/linux-5.10/drivers/thermal/tegra/ |
| D | soctherm.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014 - 2018, NVIDIA CORPORATION. All rights reserved.
34 #include <dt-bindings/thermal/tegra124-soctherm.h>
197 #define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
200 (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
203 #define THROT_DEPTH_DIVIDEND(depth) ((256 * (100 - (depth)) / 100) - 1)
205 /* gk20a nv_therm interface N:3 Mapping. Levels defined in tegra124-soctherm.h
212 #define THROT_LEVEL_TO_DEPTH(level) ((0x1 << (level)) - 1)
229 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
232 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
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