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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-pmc.txt1 NVIDIA Tegra Power Management Controller (PMC)
5 The PMC block interacts with an external Power Management Unit. The PMC
7 modes. It provides power-gating controllers for SoC and CPU power-islands.
10 - name : Should be pmc
11 - compatible : Should contain one of the following:
12 For Tegra20 must contain "nvidia,tegra20-pmc".
13 For Tegra30 must contain "nvidia,tegra30-pmc".
14 For Tegra114 must contain "nvidia,tegra114-pmc"
15 For Tegra124 must contain "nvidia,tegra124-pmc"
16 For Tegra132 must contain "nvidia,tegra124-pmc"
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra20-pmc
18 - nvidia,tegra30-pmc
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/nvidia/
Dtegra210-p2530.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "tegra210.dtsi"
5 model = "NVIDIA Tegra210 P2530 main board";
6 compatible = "nvidia,p2530", "nvidia,tegra210";
14 stdout-path = "serial0:115200n8";
29 clock-frequency = <400000>;
32 pmc@7000e400 {
33 nvidia,invert-interrupt;
39 bus-width = <8>;
40 non-removable;
[all …]
Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
[all …]
Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
[all …]
Dtegra210-p2180.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/mfd/max77620.h>
4 #include "tegra210.dtsi"
8 compatible = "nvidia,p2180", "nvidia,tegra210";
17 stdout-path = "serial0:115200n8";
26 vdd-supply = <&vdd_gpu>;
36 clock-frequency = <400000>;
41 interrupt-parent = <&tegra_pmc>;
44 #interrupt-cells = <2>;
45 interrupt-controller;
[all …]
Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
7 #include <dt-bindings/power/tegra194-powergate.h>
8 #include <dt-bindings/reset/tegra194-reset.h>
9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
10 #include <dt-bindings/memory/tegra194-mc.h>
[all …]
Dtegra210-p3450-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/linux-event-codes.h>
6 #include <dt-bindings/mfd/max77620.h>
8 #include "tegra210.dtsi"
12 compatible = "nvidia,p3450-0000", "nvidia,tegra210";
22 stdout-path = "serial0:115200n8";
33 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
34 hvddio-pex-supply = <&vdd_1v8>;
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/nvidia/
Dtegra210-p2530.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "tegra210.dtsi"
5 model = "NVIDIA Tegra210 P2530 main board";
6 compatible = "nvidia,p2530", "nvidia,tegra210";
14 stdout-path = "serial0:115200n8";
29 clock-frequency = <400000>;
32 pmc@7000e400 {
33 nvidia,invert-interrupt;
39 bus-width = <8>;
40 non-removable;
[all …]
Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 compatible = "nvidia,tegra210";
11 interrupt-parent = <&lic>;
12 #address-cells = <2>;
[all …]
Dtegra210-p2180.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/mfd/max77620.h>
4 #include "tegra210.dtsi"
8 compatible = "nvidia,p2180", "nvidia,tegra210";
17 stdout-path = "serial0:115200n8";
26 vdd-supply = <&vdd_gpu>;
36 clock-frequency = <400000>;
43 #interrupt-cells = <2>;
44 interrupt-controller;
46 #gpio-cells = <2>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/
Dnvidia,tegra124-xusb.txt8 --------------------
9 - compatible: Must be:
10 - Tegra124: "nvidia,tegra124-xusb"
11 - Tegra132: "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"
12 - Tegra210: "nvidia,tegra210-xusb"
13 - Tegra186: "nvidia,tegra186-xusb"
14 - reg: Must contain the base and length of the xHCI host registers, XUSB FPCI
16 - reg-names: Must contain the following entries:
17 - "hcd"
18 - "fpci"
[all …]
/kernel/linux/linux-4.19/drivers/clk/tegra/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += clk.o
3 obj-y += clk-audio-sync.o
4 obj-y += clk-dfll.o
5 obj-y += clk-divider.o
6 obj-y += clk-periph.o
7 obj-y += clk-periph-fixed.o
8 obj-y += clk-periph-gate.o
9 obj-y += clk-pll.o
10 obj-y += clk-pll-out.o
[all …]
Dclk-tegra210.c2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
19 #include <linux/clk-provider.h>
27 #include <dt-bindings/clock/tegra210-car.h>
28 #include <dt-bindings/reset/tegra210-car.h>
30 #include <soc/tegra/pmc.h>
33 #include "clk-id.h"
37 * banks present in the Tegra210 CAR IP block. The banks are
264 * SDM fractional divisor is 16-bit 2's complement signed number within
265 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned
266 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to
[all …]
/kernel/linux/linux-5.10/drivers/clk/tegra/
Dclk-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
8 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/tegra210-car.h>
18 #include <dt-bindings/reset/tegra210-car.h>
20 #include <soc/tegra/pmc.h>
23 #include "clk-id.h"
27 * banks present in the Tegra210 CAR IP block. The banks are
264 * SDM fractional divisor is 16-bit 2's complement signed number within
265 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/tegra/
Dvic.c20 #include <soc/tegra/pmc.h>
53 writel(value, vic->regs + offset); in vic_writel()
60 return clk_prepare_enable(vic->clk); in vic_runtime_resume()
67 clk_disable_unprepare(vic->clk); in vic_runtime_suspend()
69 vic->booted = false; in vic_runtime_suspend()
80 if (vic->booted) in vic_boot()
89 err = falcon_boot(&vic->falcon); in vic_boot()
93 hdr = vic->falcon.firmware.vaddr; in vic_boot()
95 hdr = vic->falcon.firmware.vaddr + in vic_boot()
99 falcon_execute_method(&vic->falcon, VIC_SET_APPLICATION_ID, 1); in vic_boot()
[all …]
Dsor.c10 #include <linux/clk-provider.h>
20 #include <soc/tegra/pmc.h>
33 * XXX Remove this after the commit adding it to soc/tegra/pmc.h has been
399 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl()
401 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
409 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
410 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
417 clk_disable_unprepare(sor->clk); in tegra_sor_set_parent_clock()
419 err = clk_set_parent(sor->clk_out, parent); in tegra_sor_set_parent_clock()
423 err = clk_prepare_enable(sor->clk); in tegra_sor_set_parent_clock()
[all …]
/kernel/linux/linux-4.19/drivers/soc/tegra/
Dpmc.c2 * drivers/soc/tegra/pmc.c
20 #define pr_fmt(fmt) "tegra-pmc: " fmt
46 #include <soc/tegra/pmc.h>
129 struct tegra_pmc *pmc; member
165 void (*init)(struct tegra_pmc *pmc);
166 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
172 * struct tegra_pmc - NVIDIA Tegra PMC
173 * @dev: pointer to PMC device structure
185 * @corereq_high: core power request is active-high
186 * @sysclkreq_high: system clock request is active-high
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/tegra/
Dvic.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <soc/tegra/pmc.h>
52 writel(value, vic->regs + offset); in vic_writel()
60 err = clk_prepare_enable(vic->clk); in vic_runtime_resume()
66 err = reset_control_deassert(vic->rst); in vic_runtime_resume()
75 clk_disable_unprepare(vic->clk); in vic_runtime_resume()
84 err = reset_control_assert(vic->rst); in vic_runtime_suspend()
90 clk_disable_unprepare(vic->clk); in vic_runtime_suspend()
92 vic->booted = false; in vic_runtime_suspend()
100 struct iommu_fwspec *spec = dev_iommu_fwspec_get(vic->dev); in vic_boot()
[all …]
Dsor.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
17 #include <soc/tegra/pmc.h>
486 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl()
488 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
496 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
497 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
504 clk_disable_unprepare(sor->clk); in tegra_sor_set_parent_clock()
506 err = clk_set_parent(sor->clk_out, parent); in tegra_sor_set_parent_clock()
510 err = clk_prepare_enable(sor->clk); in tegra_sor_set_parent_clock()
[all …]
/kernel/linux/linux-5.10/drivers/soc/tegra/
Dpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/soc/tegra/pmc.c
6 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
36 #include <linux/pinctrl/pinconf-generic.h>
49 #include <soc/tegra/pmc.h>
51 #include <dt-bindings/interrupt-controller/arm-gic.h>
[all …]
/kernel/linux/linux-5.10/drivers/ata/
Dahci_tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <soc/tegra/pmc.h>
25 #define DRV_NAME "tegra-ahci"
179 struct tegra_ahci_priv *tegra = hpriv->plat_data; in tegra_ahci_handle_quirks()
182 if (tegra->sata_aux_regs && !tegra->soc->supports_devslp) { in tegra_ahci_handle_quirks()
183 val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); in tegra_ahci_handle_quirks()
185 writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); in tegra_ahci_handle_quirks()
191 struct tegra_ahci_priv *tegra = hpriv->plat_data; in tegra124_ahci_init()
203 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); in tegra124_ahci_init()
205 val = readl(tegra->sata_regs + in tegra124_ahci_init()
[all …]
/kernel/linux/linux-4.19/drivers/ata/
Dahci_tegra.c30 #include <soc/tegra/pmc.h>
34 #define DRV_NAME "tegra-ahci"
188 struct tegra_ahci_priv *tegra = hpriv->plat_data; in tegra_ahci_handle_quirks()
191 if (tegra->sata_aux_regs && !tegra->soc->supports_devslp) { in tegra_ahci_handle_quirks()
192 val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); in tegra_ahci_handle_quirks()
194 writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); in tegra_ahci_handle_quirks()
200 struct tegra_ahci_priv *tegra = hpriv->plat_data; in tegra124_ahci_init()
212 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); in tegra124_ahci_init()
214 val = readl(tegra->sata_regs + in tegra124_ahci_init()
220 writel(val, tegra->sata_regs + SCFG_OFFSET + in tegra124_ahci_init()
[all …]
/kernel/linux/linux-4.19/drivers/usb/host/
Dxhci-tegra.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/dma-mapping.h>
25 #include <soc/tegra/pmc.h>
212 return readl(tegra->fpci_base + offset); in fpci_readl()
218 writel(value, tegra->fpci_base + offset); in fpci_writel()
223 return readl(tegra->ipfs_base + offset); in ipfs_readl()
229 writel(value, tegra->ipfs_base + offset); in ipfs_writel()
256 struct clk *clk = tegra->ss_src_clk; in tegra_xusb_set_ss_clk()
270 new_parent_rate = clk_get_rate(tegra->pll_u_480m); in tegra_xusb_set_ss_clk()
277 err = clk_set_parent(clk, tegra->pll_u_480m); in tegra_xusb_set_ss_clk()
[all …]
/kernel/linux/linux-5.10/drivers/usb/host/
Dxhci-tegra.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/dma-mapping.h>
30 #include <soc/tegra/pmc.h>
280 return readl(tegra->fpci_base + offset); in fpci_readl()
286 writel(value, tegra->fpci_base + offset); in fpci_writel()
291 return readl(tegra->ipfs_base + offset); in ipfs_readl()
297 writel(value, tegra->ipfs_base + offset); in ipfs_writel()
324 struct clk *clk = tegra->ss_src_clk; in tegra_xusb_set_ss_clk()
338 new_parent_rate = clk_get_rate(tegra->pll_u_480m); in tegra_xusb_set_ss_clk()
345 err = clk_set_parent(clk, tegra->pll_u_480m); in tegra_xusb_set_ss_clk()
[all …]

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