| /kernel/linux/linux-5.10/drivers/gpu/drm/tegra/ |
| D | mipi-phy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include "mipi-phy.h"
12 * Default D-PHY timings based on MIPI D-PHY specification. Derived from the
13 * valid ranges specified in Section 6.9, Table 14, Page 40 of the D-PHY
16 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, in mipi_dphy_timing_get_default() argument
19 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
20 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
21 timing->clkpre = 8; in mipi_dphy_timing_get_default()
22 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
23 timing->clksettle = 95; in mipi_dphy_timing_get_default()
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| /kernel/linux/linux-4.19/drivers/gpu/drm/tegra/ |
| D | mipi-phy.c | 12 #include "mipi-phy.h"
15 * Default D-PHY timings based on MIPI D-PHY specification. Derived from the
16 * valid ranges specified in Section 6.9, Table 14, Page 40 of the D-PHY
19 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, in mipi_dphy_timing_get_default() argument
22 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
23 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
24 timing->clkpre = 8; in mipi_dphy_timing_get_default()
25 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
26 timing->clksettle = 95; in mipi_dphy_timing_get_default()
27 timing->clktermen = 0; in mipi_dphy_timing_get_default()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/phy/ |
| D | dsi_phy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
18 v = (tmax - tmin) * percent; in linear_inter()
20 if (even && (v & 0x1)) in linear_inter()
21 return max_t(s32, min_result, v - 1); in linear_inter()
26 static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing, in dsi_dphy_timing_calc_clk_zero() argument
33 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
34 tmin = S_DIV_ROUND_UP(temp, ui) - 2; in dsi_dphy_timing_calc_clk_zero()
37 clk_z = linear_inter(2 * tmin, tmin, pcnt, 0, true); in dsi_dphy_timing_calc_clk_zero()
40 clk_z = linear_inter(tmax, tmin, pcnt, 0, true); in dsi_dphy_timing_calc_clk_zero()
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| D | dsi_phy_14nm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 struct msm_dsi_dphy_timing *timing, in dsi_14nm_dphy_set_timing() argument
17 void __iomem *base = phy->lane_base; in dsi_14nm_dphy_set_timing()
19 u32 zero = clk_ln ? timing->clk_zero : timing->hs_zero; in dsi_14nm_dphy_set_timing()
20 u32 prepare = clk_ln ? timing->clk_prepare : timing->hs_prepare; in dsi_14nm_dphy_set_timing()
21 u32 trail = clk_ln ? timing->clk_trail : timing->hs_trail; in dsi_14nm_dphy_set_timing()
22 u32 rqst = clk_ln ? timing->hs_rqst_ckln : timing->hs_rqst; in dsi_14nm_dphy_set_timing()
23 u32 prep_dly = clk_ln ? timing->hs_prep_dly_ckln : timing->hs_prep_dly; in dsi_14nm_dphy_set_timing()
24 u32 halfbyte_en = clk_ln ? timing->hs_halfbyte_en_ckln : in dsi_14nm_dphy_set_timing()
25 timing->hs_halfbyte_en; in dsi_14nm_dphy_set_timing()
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| D | dsi_phy_20nm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 struct msm_dsi_dphy_timing *timing) in dsi_20nm_dphy_set_timing() argument
12 void __iomem *base = phy->base; in dsi_20nm_dphy_set_timing()
15 DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_20nm_dphy_set_timing()
17 DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); in dsi_20nm_dphy_set_timing()
19 DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); in dsi_20nm_dphy_set_timing()
20 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
24 DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_20nm_dphy_set_timing()
26 DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); in dsi_20nm_dphy_set_timing()
28 DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); in dsi_20nm_dphy_set_timing()
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| /kernel/linux/linux-4.19/drivers/gpu/drm/msm/dsi/phy/ |
| D | dsi_phy.c | 19 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
26 v = (tmax - tmin) * percent; in linear_inter()
28 if (even && (v & 0x1)) in linear_inter()
29 return max_t(s32, min_result, v - 1); in linear_inter()
34 static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing, in dsi_dphy_timing_calc_clk_zero() argument
41 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
42 tmin = S_DIV_ROUND_UP(temp, ui) - 2; in dsi_dphy_timing_calc_clk_zero()
45 clk_z = linear_inter(2 * tmin, tmin, pcnt, 0, true); in dsi_dphy_timing_calc_clk_zero()
48 clk_z = linear_inter(tmax, tmin, pcnt, 0, true); in dsi_dphy_timing_calc_clk_zero()
52 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7; in dsi_dphy_timing_calc_clk_zero()
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| D | dsi_phy_14nm.c | 20 struct msm_dsi_dphy_timing *timing, in dsi_14nm_dphy_set_timing() argument
23 void __iomem *base = phy->lane_base; in dsi_14nm_dphy_set_timing()
25 u32 zero = clk_ln ? timing->clk_zero : timing->hs_zero; in dsi_14nm_dphy_set_timing()
26 u32 prepare = clk_ln ? timing->clk_prepare : timing->hs_prepare; in dsi_14nm_dphy_set_timing()
27 u32 trail = clk_ln ? timing->clk_trail : timing->hs_trail; in dsi_14nm_dphy_set_timing()
28 u32 rqst = clk_ln ? timing->hs_rqst_ckln : timing->hs_rqst; in dsi_14nm_dphy_set_timing()
29 u32 prep_dly = clk_ln ? timing->hs_prep_dly_ckln : timing->hs_prep_dly; in dsi_14nm_dphy_set_timing()
30 u32 halfbyte_en = clk_ln ? timing->hs_halfbyte_en_ckln : in dsi_14nm_dphy_set_timing()
31 timing->hs_halfbyte_en; in dsi_14nm_dphy_set_timing()
34 DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_14nm_dphy_set_timing()
[all …]
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| D | dsi_phy_20nm.c | 18 struct msm_dsi_dphy_timing *timing) in dsi_20nm_dphy_set_timing() argument
20 void __iomem *base = phy->base; in dsi_20nm_dphy_set_timing()
23 DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_20nm_dphy_set_timing()
25 DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); in dsi_20nm_dphy_set_timing()
27 DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); in dsi_20nm_dphy_set_timing()
28 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
32 DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_20nm_dphy_set_timing()
34 DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); in dsi_20nm_dphy_set_timing()
36 DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); in dsi_20nm_dphy_set_timing()
38 DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail)); in dsi_20nm_dphy_set_timing()
[all …]
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| D | dsi_phy_28nm.c | 18 struct msm_dsi_dphy_timing *timing) in dsi_28nm_dphy_set_timing() argument
20 void __iomem *base = phy->base; in dsi_28nm_dphy_set_timing()
23 DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_28nm_dphy_set_timing()
25 DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); in dsi_28nm_dphy_set_timing()
27 DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); in dsi_28nm_dphy_set_timing()
28 if (timing->clk_zero & BIT(8)) in dsi_28nm_dphy_set_timing()
32 DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_28nm_dphy_set_timing()
34 DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); in dsi_28nm_dphy_set_timing()
36 DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); in dsi_28nm_dphy_set_timing()
38 DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail)); in dsi_28nm_dphy_set_timing()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/tegra/ |
| D | clk-tegra124-emc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
28 #define CLK_SOURCE_EMC 0x19c
30 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0
31 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff
36 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7
47 * When we change the timing to a timing with a parent that has the same
49 * timing that has a different clock source.
52 #define EMC_SRC_PLL_M 0
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| /kernel/linux/linux-4.19/drivers/clk/tegra/ |
| D | clk-emc.c | 2 * drivers/clk/tegra/clk-emc.c
19 #include <linux/clk-provider.h>
35 #define CLK_SOURCE_EMC 0x19c
37 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0
38 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff
43 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7
54 * When we change the timing to a timing with a parent that has the same
56 * timing that has a different clock source.
59 #define EMC_SRC_PLL_M 0
108 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
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| /kernel/linux/linux-4.19/drivers/memory/tegra/ |
| D | tegra124-emc.c | 18 #include <linux/clk-provider.h>
33 #define EMC_FBIO_CFG5 0x104
34 #define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
35 #define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0
37 #define EMC_INTSTATUS 0x0
40 #define EMC_CFG 0xc
45 #define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18))
48 #define EMC_REFCTRL 0x20
49 #define EMC_REFCTRL_DEV_SEL_SHIFT 0
52 #define EMC_TIMING_CONTROL 0x28
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| /kernel/linux/linux-4.19/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| D | timing.c | 26 #include <subdev/bios/timing.h>
33 u32 timing = 0; in nvbios_timingTe() local
37 timing = nvbios_rd32(bios, bit_P.offset + 4); in nvbios_timingTe()
40 timing = nvbios_rd32(bios, bit_P.offset + 8); in nvbios_timingTe()
42 if (timing) { in nvbios_timingTe()
43 *ver = nvbios_rd08(bios, timing + 0); in nvbios_timingTe()
45 case 0x10: in nvbios_timingTe()
46 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
47 *cnt = nvbios_rd08(bios, timing + 2); in nvbios_timingTe()
48 *len = nvbios_rd08(bios, timing + 3); in nvbios_timingTe()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| D | timing.c | 26 #include <subdev/bios/timing.h>
33 u32 timing = 0; in nvbios_timingTe() local
37 timing = nvbios_rd32(bios, bit_P.offset + 4); in nvbios_timingTe()
40 timing = nvbios_rd32(bios, bit_P.offset + 8); in nvbios_timingTe()
42 if (timing) { in nvbios_timingTe()
43 *ver = nvbios_rd08(bios, timing + 0); in nvbios_timingTe()
45 case 0x10: in nvbios_timingTe()
46 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
47 *cnt = nvbios_rd08(bios, timing + 2); in nvbios_timingTe()
48 *len = nvbios_rd08(bios, timing + 3); in nvbios_timingTe()
[all …]
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| /kernel/linux/linux-5.10/drivers/memory/tegra/ |
| D | tegra124-emc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
25 #define EMC_FBIO_CFG5 0x104
26 #define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
27 #define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0
29 #define EMC_INTSTATUS 0x0
32 #define EMC_CFG 0xc
37 #define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18))
40 #define EMC_REFCTRL 0x20
41 #define EMC_REFCTRL_DEV_SEL_SHIFT 0
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| /kernel/linux/linux-5.10/drivers/devfreq/ |
| D | rk3399_dmc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Lin Huang <hl@rock-chips.com>
7 #include <linux/arm-smccc.h>
11 #include <linux/devfreq-event.h>
65 struct dram_timing timing; member
79 unsigned long old_clk_rate = dmcfreq->rate; in rk3399_dmcfreq_target()
93 if (dmcfreq->rate == target_rate) in rk3399_dmcfreq_target()
94 return 0; in rk3399_dmcfreq_target()
96 mutex_lock(&dmcfreq->lock); in rk3399_dmcfreq_target()
98 if (dmcfreq->regmap_pmu) { in rk3399_dmcfreq_target()
[all …]
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| /kernel/linux/linux-5.10/drivers/video/fbdev/ |
| D | gbefb.c | 4 * Copyright (C) 1999 Silicon Graphics, Inc. - Jeffrey Newquist
5 * Copyright (C) 2002 Vivien Chappelier <vivien.chappelier@linux-mips.org>
14 #include <linux/dma-mapping.h>
37 struct gbe_timing_info timing; member
42 #define GBE_BASE 0x16000000 /* SGI O2 */
44 /* macro for fastest write-though access to the framebuffer */
63 #define TILE_MASK (TILE_SIZE - 1)
81 static int gbe_turned_on; /* 0 turned off, 1 turned on */
87 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
92 .xoffset = 0,
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| /kernel/linux/linux-5.10/drivers/video/fbdev/via/ |
| D | via_modesetting.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
12 #include <linux/via-core.h>
18 void via_set_primary_timing(const struct via_display_timing *timing) in via_set_primary_timing() argument
22 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
23 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
24 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; in via_set_primary_timing()
25 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; in via_set_primary_timing()
26 raw.hor_sync_start = timing->hor_sync_start / 8; in via_set_primary_timing()
[all …]
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| /kernel/linux/linux-4.19/drivers/devfreq/ |
| D | rk3399_dmc.c | 3 * Author: Lin Huang <hl@rock-chips.com>
15 #include <linux/arm-smccc.h>
19 #include <linux/devfreq-event.h>
70 struct dram_timing timing; member
81 unsigned long old_clk_rate = dmcfreq->rate; in rk3399_dmcfreq_target()
93 if (dmcfreq->rate == target_rate) in rk3399_dmcfreq_target()
94 return 0; in rk3399_dmcfreq_target()
96 mutex_lock(&dmcfreq->lock); in rk3399_dmcfreq_target()
103 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt, in rk3399_dmcfreq_target()
112 err = clk_set_rate(dmcfreq->dmc_clk, target_rate); in rk3399_dmcfreq_target()
[all …]
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| /kernel/linux/linux-4.19/drivers/video/fbdev/ |
| D | gbefb.c | 4 * Copyright (C) 1999 Silicon Graphics, Inc. - Jeffrey Newquist
5 * Copyright (C) 2002 Vivien Chappelier <vivien.chappelier@linux-mips.org>
14 #include <linux/dma-mapping.h>
37 struct gbe_timing_info timing; member
43 #define GBE_BASE 0x16000000 /* SGI O2 */
46 /* macro for fastest write-though access to the framebuffer */
69 #define TILE_MASK (TILE_SIZE - 1)
87 static int gbe_turned_on; /* 0 turned off, 1 turned on */
93 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
98 .xoffset = 0,
[all …]
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| /kernel/linux/linux-4.19/drivers/video/fbdev/via/ |
| D | via_modesetting.c | 2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 #include <linux/via-core.h>
33 void via_set_primary_timing(const struct via_display_timing *timing) in via_set_primary_timing() argument
37 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
38 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
39 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; in via_set_primary_timing()
40 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; in via_set_primary_timing()
41 raw.hor_sync_start = timing->hor_sync_start / 8; in via_set_primary_timing()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_encoder_phys_vid.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
13 (e) && (e)->parent ? \
14 (e)->parent->base.id : -1, \
15 (e) && (e)->hw_intf ? \
16 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
19 (e) && (e)->parent ? \
20 (e)->parent->base.id : -1, \
21 (e) && (e)->hw_intf ? \
22 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
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| /kernel/linux/linux-5.10/drivers/gpu/drm/sti/ |
| D | sti_awg_utils.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #define AWG_DELAY (-5)
14 #define AWG_MAX_ARG 0x3ff
34 u32 instruction = 0; in awg_generate_instr()
35 u32 mux = (mux_sel << 8) & 0x1ff; in awg_generate_instr()
36 u32 data_enable = (data_en << 9) & 0x2ff; in awg_generate_instr()
46 while (arg_tmp > 0) { in awg_generate_instr()
48 if (fwparams->instruction_offset >= AWG_MAX_INST) { in awg_generate_instr()
50 return -EINVAL; in awg_generate_instr()
57 arg--; /* pixel adjustment */ in awg_generate_instr()
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| /kernel/linux/linux-4.19/drivers/gpu/drm/sti/ |
| D | sti_awg_utils.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #define AWG_DELAY (-5)
12 #define AWG_MAX_ARG 0x3ff
32 u32 instruction = 0; in awg_generate_instr()
33 u32 mux = (mux_sel << 8) & 0x1ff; in awg_generate_instr()
34 u32 data_enable = (data_en << 9) & 0x2ff; in awg_generate_instr()
44 while (arg_tmp > 0) { in awg_generate_instr()
46 if (fwparams->instruction_offset >= AWG_MAX_INST) { in awg_generate_instr()
48 return -EINVAL; in awg_generate_instr()
55 arg--; /* pixel adjustment */ in awg_generate_instr()
[all …]
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| /kernel/linux/linux-4.19/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | ramnv50.c | 34 #include <subdev/bios/timing.h>
71 #define T(t) cfg->timing_10_##t
73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_calc() argument
75 struct nvbios_ramcfg *cfg = &ram->base.target.bios; in nv50_ram_timing_calc()
76 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in nv50_ram_timing_calc()
77 struct nvkm_device *device = subdev->device; in nv50_ram_timing_calc()
81 cur2 = nvkm_rd32(device, 0x100228); in nv50_ram_timing_calc()
82 cur4 = nvkm_rd32(device, 0x100230); in nv50_ram_timing_calc()
83 cur7 = nvkm_rd32(device, 0x10023c); in nv50_ram_timing_calc()
84 cur8 = nvkm_rd32(device, 0x100240); in nv50_ram_timing_calc()
[all …]
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