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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,topckgen.txt1 Mediatek topckgen controller
4 The Mediatek topckgen controller provides various clocks to the system.
9 - "mediatek,mt2701-topckgen"
10 - "mediatek,mt2712-topckgen", "syscon"
11 - "mediatek,mt6765-topckgen", "syscon"
12 - "mediatek,mt6779-topckgen", "syscon"
13 - "mediatek,mt6797-topckgen"
14 - "mediatek,mt7622-topckgen"
15 - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
16 - "mediatek,mt7629-topckgen"
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/sound/
Dmt2701-afe-pcm.txt69 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
70 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
71 <&topckgen CLK_TOP_AUD_48K_TIMING>,
72 <&topckgen CLK_TOP_AUD_44K_TIMING>,
73 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
74 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
75 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
76 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
77 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
78 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
[all …]
Dmtk-afe-pcm.txt26 <&topckgen TOP_AUDIO_SEL>,
27 <&topckgen TOP_AUD_INTBUS_SEL>,
28 <&topckgen TOP_APLL1_DIV0>,
29 <&topckgen TOP_APLL2_DIV0>,
30 <&topckgen TOP_I2S0_M_CK_SEL>,
31 <&topckgen TOP_I2S1_M_CK_SEL>,
32 <&topckgen TOP_I2S2_M_CK_SEL>,
33 <&topckgen TOP_I2S3_M_CK_SEL>,
34 <&topckgen TOP_I2S3_B_CK_SEL>;
Dmt6797-afe-pcm.txt29 <&topckgen CLK_TOP_MUX_AUDIO>,
30 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
31 <&topckgen CLK_TOP_SYSPLL3_D4>,
32 <&topckgen CLK_TOP_SYSPLL1_D4>,
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/
Dmt2701-afe-pcm.txt69 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
70 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
71 <&topckgen CLK_TOP_AUD_48K_TIMING>,
72 <&topckgen CLK_TOP_AUD_44K_TIMING>,
73 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
74 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
75 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
76 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
77 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
78 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
[all …]
Dmtk-afe-pcm.txt26 <&topckgen TOP_AUDIO_SEL>,
27 <&topckgen TOP_AUD_INTBUS_SEL>,
28 <&topckgen TOP_APLL1_DIV0>,
29 <&topckgen TOP_APLL2_DIV0>,
30 <&topckgen TOP_I2S0_M_CK_SEL>,
31 <&topckgen TOP_I2S1_M_CK_SEL>,
32 <&topckgen TOP_I2S2_M_CK_SEL>,
33 <&topckgen TOP_I2S3_M_CK_SEL>,
34 <&topckgen TOP_I2S3_B_CK_SEL>;
Dmt6797-afe-pcm.txt29 <&topckgen CLK_TOP_MUX_AUDIO>,
30 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
31 <&topckgen CLK_TOP_SYSPLL3_D4>,
32 <&topckgen CLK_TOP_SYSPLL1_D4>,
/kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/
Dmt8516.dtsi58 <&topckgen CLK_TOP_MAINPLL_D2>;
71 <&topckgen CLK_TOP_MAINPLL_D2>;
84 <&topckgen CLK_TOP_MAINPLL_D2>;
97 <&topckgen CLK_TOP_MAINPLL_D2>;
182 topckgen: topckgen@10000000 { label
183 compatible = "mediatek,mt8516-topckgen", "syscon";
218 clocks = <&topckgen CLK_TOP_CLK26M_D2>,
219 <&topckgen CLK_TOP_APXGPT>;
245 clocks = <&topckgen CLK_TOP_PMICWRAP_26M>,
246 <&topckgen CLK_TOP_PMICWRAP_AP>;
[all …]
Dmt7622.dtsi243 clocks = <&topckgen CLK_TOP_HIF_SEL>;
252 <&topckgen CLK_TOP_AXI_SEL>;
285 topckgen: topckgen@10210000 { label
286 compatible = "mediatek,mt7622-topckgen",
325 clocks = <&topckgen CLK_TOP_RTC>;
389 clocks = <&topckgen CLK_TOP_UART_SEL>,
400 clocks = <&topckgen CLK_TOP_UART_SEL>,
411 clocks = <&topckgen CLK_TOP_UART_SEL>,
422 clocks = <&topckgen CLK_TOP_UART_SEL>,
432 clocks = <&topckgen CLK_TOP_PWM_SEL>,
[all …]
Dmt8173.dtsi356 topckgen: clock-controller@10000000 { label
357 compatible = "mediatek,mt8173-topckgen";
458 <&topckgen CLK_TOP_MM_SEL>,
459 <&topckgen CLK_TOP_VENC_SEL>,
460 <&topckgen CLK_TOP_VENC_LT_SEL>;
477 <&topckgen CLK_TOP_RTC_SEL>;
505 clocks = <&topckgen CLK_TOP_SCP_SEL>;
703 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
704 <&topckgen CLK_TOP_SPI_SEL>,
728 <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
[all …]
Dmt2712e.dtsi90 <&topckgen CLK_TOP_F_MP0_PLL1>;
103 <&topckgen CLK_TOP_F_MP0_PLL1>;
116 <&topckgen CLK_TOP_F_BIG_PLL1>;
246 topckgen: syscon@10000000 { label
247 compatible = "mediatek,mt2712-topckgen", "syscon";
285 clocks = <&topckgen CLK_TOP_MM_SEL>,
286 <&topckgen CLK_TOP_MFG_SEL>,
287 <&topckgen CLK_TOP_VENC_SEL>,
288 <&topckgen CLK_TOP_JPGDEC_SEL>,
289 <&topckgen CLK_TOP_A1SYS_HP_SEL>,
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/
Dmediatek-vcodec.txt57 <&topckgen CLK_TOP_UNIVPLL_D2>,
58 <&topckgen CLK_TOP_CCI400_SEL>,
59 <&topckgen CLK_TOP_VDEC_SEL>,
60 <&topckgen CLK_TOP_VCODECPLL>,
62 <&topckgen CLK_TOP_VENC_LT_SEL>,
63 <&topckgen CLK_TOP_VCODECPLL_370P5>;
72 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
73 <&topckgen CLK_TOP_CCI400_SEL>,
74 <&topckgen CLK_TOP_VDEC_SEL>,
77 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,topckgen.txt1 Mediatek topckgen controller
4 The Mediatek topckgen controller provides various clocks to the system.
9 - "mediatek,mt2701-topckgen"
10 - "mediatek,mt2712-topckgen", "syscon"
11 - "mediatek,mt6797-topckgen"
12 - "mediatek,mt7622-topckgen"
13 - "mediatek,mt8135-topckgen"
14 - "mediatek,mt8173-topckgen"
17 The topckgen controller uses the common clk binding from
23 topckgen: power-controller@10000000 {
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dmt7629.dtsi98 clocks = <&topckgen CLK_TOP_HIF_SEL>;
100 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
138 topckgen: syscon@10210000 { label
139 compatible = "mediatek,mt7629-topckgen", "syscon";
216 clocks = <&topckgen CLK_TOP_UART_SEL>,
227 clocks = <&topckgen CLK_TOP_UART_SEL>,
238 clocks = <&topckgen CLK_TOP_UART_SEL>,
248 clocks = <&topckgen CLK_TOP_PWM_SEL>,
252 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
[all …]
Dmt2701.dtsi126 topckgen: syscon@10000000 { label
127 compatible = "mediatek,mt2701-topckgen", "syscon";
156 clocks = <&topckgen CLK_TOP_MM_SEL>,
157 <&topckgen CLK_TOP_MFG_SEL>,
158 <&topckgen CLK_TOP_ETHIF_SEL>;
343 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
344 <&topckgen CLK_TOP_SPI0_SEL>,
390 <&topckgen CLK_TOP_FLASH_SEL>;
403 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
404 <&topckgen CLK_TOP_SPI1_SEL>,
[all …]
Dmt7623.dtsi226 topckgen: syscon@10000000 { label
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
278 clocks = <&topckgen CLK_TOP_MM_SEL>,
279 <&topckgen CLK_TOP_MFG_SEL>,
280 <&topckgen CLK_TOP_ETHIF_SEL>;
424 clocks = <&topckgen CLK_TOP_PWM_SEL>,
488 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
489 <&topckgen CLK_TOP_SPI0_SEL>,
553 <&topckgen CLK_TOP_FLASH_SEL>;
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dmt2701.dtsi125 topckgen: syscon@10000000 { label
126 compatible = "mediatek,mt2701-topckgen", "syscon";
155 clocks = <&topckgen CLK_TOP_MM_SEL>,
156 <&topckgen CLK_TOP_MFG_SEL>,
157 <&topckgen CLK_TOP_ETHIF_SEL>;
342 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
343 <&topckgen CLK_TOP_SPI0_SEL>,
389 <&topckgen CLK_TOP_FLASH_SEL>;
402 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
403 <&topckgen CLK_TOP_SPI1_SEL>,
[all …]
Dmt7623.dtsi207 topckgen: syscon@10000000 { label
208 compatible = "mediatek,mt7623-topckgen",
209 "mediatek,mt2701-topckgen",
259 clocks = <&topckgen CLK_TOP_MM_SEL>,
260 <&topckgen CLK_TOP_MFG_SEL>,
261 <&topckgen CLK_TOP_ETHIF_SEL>;
405 clocks = <&topckgen CLK_TOP_PWM_SEL>,
469 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
470 <&topckgen CLK_TOP_SPI0_SEL>,
534 <&topckgen CLK_TOP_FLASH_SEL>;
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/mediatek/
Dmt7622.dtsi231 clocks = <&topckgen CLK_TOP_HIF_SEL>;
240 <&topckgen CLK_TOP_AXI_SEL>;
273 topckgen: topckgen@10210000 { label
274 compatible = "mediatek,mt7622-topckgen",
313 clocks = <&topckgen CLK_TOP_RTC>;
341 clocks = <&topckgen CLK_TOP_UART_SEL>,
352 clocks = <&topckgen CLK_TOP_UART_SEL>,
363 clocks = <&topckgen CLK_TOP_UART_SEL>,
374 clocks = <&topckgen CLK_TOP_UART_SEL>,
384 clocks = <&topckgen CLK_TOP_PWM_SEL>,
[all …]
Dmt8173.dtsi321 topckgen: clock-controller@10000000 { label
322 compatible = "mediatek,mt8173-topckgen";
423 <&topckgen CLK_TOP_MM_SEL>,
424 <&topckgen CLK_TOP_VENC_SEL>,
425 <&topckgen CLK_TOP_VENC_LT_SEL>;
442 <&topckgen CLK_TOP_RTC_SEL>;
470 clocks = <&topckgen CLK_TOP_SCP_SEL>;
659 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
660 <&topckgen CLK_TOP_SPI_SEL>,
684 <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/media/
Dmediatek-vcodec.txt54 <&topckgen CLK_TOP_UNIVPLL_D2>,
55 <&topckgen CLK_TOP_CCI400_SEL>,
56 <&topckgen CLK_TOP_VDEC_SEL>,
57 <&topckgen CLK_TOP_VCODECPLL>,
59 <&topckgen CLK_TOP_VENC_LT_SEL>,
60 <&topckgen CLK_TOP_VCODECPLL_370P5>;
100 clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
101 <&topckgen CLK_TOP_VENC_SEL>,
102 <&topckgen CLK_TOP_UNIVPLL1_D2>,
103 <&topckgen CLK_TOP_VENC_LT_SEL>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/
Dspi-slave-mt27xx.txt13 - assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>.
16 - <&topckgen CLK_TOP_UNIVPLL1_D2>: specify parent clock 312MHZ.
18 - <&topckgen CLK_TOP_UNIVPLL1_D4>: specify parent clock 156MHZ.
19 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
20 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
30 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
31 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
Dspi-mt65xx.txt28 - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
30 - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
31 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
32 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
33 The second should be <&topckgen CLK_TOP_SPI_SEL>. It's clock mux.
59 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
60 <&topckgen CLK_TOP_SPI_SEL>,
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dmediatek-dwmac.txt71 <&topckgen CLK_TOP_ETHER_125M_SEL>,
72 <&topckgen CLK_TOP_ETHER_50M_SEL>,
73 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
74 assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
75 <&topckgen CLK_TOP_ETHER_50M_SEL>,
76 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
77 assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
78 <&topckgen CLK_TOP_APLL1_D3>,
79 <&topckgen CLK_TOP_ETHERPLL_50M>;
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/spi/
Dspi-mt65xx.txt23 - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
25 - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
26 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
27 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
28 The second should be <&topckgen CLK_TOP_SPI_SEL>. It's clock mux.
54 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
55 <&topckgen CLK_TOP_SPI_SEL>,

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