| /kernel/linux/linux-5.10/drivers/tty/serial/8250/ |
| D | 8250_ingenic.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
6 * Ingenic SoC UART support
27 int fifosize; member
47 return readl(port->membase + (offset << 2)); in early_in()
52 writel(value, port->membase + (offset << 2)); in early_out()
69 uart_console_write(&early_device->port, s, count, in ingenic_early_console_write()
83 prop = fdt_getprop(fdt, offset, "clock-frequency", NULL); in ingenic_early_console_setup_clock()
87 dev->port.uartclk = be32_to_cpup(prop); in ingenic_early_console_setup_clock()
93 struct uart_port *port = &dev->port; in ingenic_early_console_setup()
[all …]
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| D | 8250_of.c | 1 // SPDX-License-Identifier: GPL-2.0+
36 struct device_node *np = ofdev->dev.of_node; in of_platform_serial_setup()
37 struct uart_port *port = &up->port; in of_platform_serial_setup()
43 pm_runtime_enable(&ofdev->dev); in of_platform_serial_setup()
44 pm_runtime_get_sync(&ofdev->dev); in of_platform_serial_setup()
46 if (of_property_read_u32(np, "clock-frequency", &clk)) { in of_platform_serial_setup()
49 info->clk = devm_clk_get(&ofdev->dev, NULL); in of_platform_serial_setup()
50 if (IS_ERR(info->clk)) { in of_platform_serial_setup()
51 ret = PTR_ERR(info->clk); in of_platform_serial_setup()
52 if (ret != -EPROBE_DEFER) in of_platform_serial_setup()
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| D | 8250_core.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Universal/legacy driver for 8250/16550-type serial ports
9 * Supports: ISA-compatible 8250/16550 ports
12 * userspace-configurable "phantom" ports
47 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
48 * is unsafe when used on edge-triggered interrupts.
62 * SERIAL_PORT_DFNS tells us about built-in ports that have no
103 * line has been de-asserted.
116 spin_lock(&i->lock); in serial8250_interrupt()
118 l = i->head; in serial8250_interrupt()
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| /kernel/linux/linux-4.19/drivers/tty/serial/8250/ |
| D | 8250_ingenic.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
6 * Ingenic SoC UART support
27 int fifosize; member
47 return readl(port->membase + (offset << 2)); in early_in()
52 writel(value, port->membase + (offset << 2)); in early_out()
69 uart_console_write(&early_device->port, s, count, in ingenic_early_console_write()
83 prop = fdt_getprop(fdt, offset, "clock-frequency", NULL); in ingenic_early_console_setup_clock()
87 dev->port.uartclk = be32_to_cpup(prop); in ingenic_early_console_setup_clock()
93 struct uart_port *port = &dev->port; in ingenic_early_console_setup()
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| D | 8250_of.c | 1 // SPDX-License-Identifier: GPL-2.0+
35 status = p->serial_in(p, UART_LSR); in tegra_serial_handle_break()
37 status = p->serial_in(p, UART_RX); in tegra_serial_handle_break()
40 if (--tmout == 0) in tegra_serial_handle_break()
59 struct device_node *np = ofdev->dev.of_node; in of_platform_serial_setup()
65 pm_runtime_enable(&ofdev->dev); in of_platform_serial_setup()
66 pm_runtime_get_sync(&ofdev->dev); in of_platform_serial_setup()
68 if (of_property_read_u32(np, "clock-frequency", &clk)) { in of_platform_serial_setup()
71 info->clk = devm_clk_get(&ofdev->dev, NULL); in of_platform_serial_setup()
72 if (IS_ERR(info->clk)) { in of_platform_serial_setup()
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| D | 8250_core.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Universal/legacy driver for 8250/16550-type serial ports
9 * Supports: ISA-compatible 8250/16550 ports
12 * userspace-configurable "phantom" ports
46 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
47 * is unsafe when used on edge-triggered interrupts.
61 * SERIAL_PORT_DFNS tells us about built-in ports that have no
102 * line has been de-asserted.
115 spin_lock(&i->lock); in serial8250_interrupt()
117 l = i->head; in serial8250_interrupt()
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| D | 8250_dw.c | 1 // SPDX-License-Identifier: GPL-2.0+
10 * raised, the LCR needs to be rewritten and the uart status register read.
33 #define DW_UART_USR 0x1f /* UART Status Register */
36 #define DW_UART_UCV 0xf8 /* UART Component Version */
74 if (p->iotype == UPIO_MEM32BE) in dw8250_readl_ext()
75 return ioread32be(p->membase + offset); in dw8250_readl_ext()
76 return readl(p->membase + offset); in dw8250_readl_ext()
81 if (p->iotype == UPIO_MEM32BE) in dw8250_writel_ext()
82 iowrite32be(reg, p->membase + offset); in dw8250_writel_ext()
84 writel(reg, p->membase + offset); in dw8250_writel_ext()
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/serial/ |
| D | sirf-uart.txt | 4 - compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart",
5 "sirf,atlas7-uart" or "sirf,atlas7-usp-uart".
6 - reg : Offset and length of the register set for the device
7 - interrupts : Should contain uart interrupt
8 - fifosize : Should define hardware rx/tx fifo size
9 - clocks : Should contain uart clock number
12 - uart-has-rtscts: we have hardware flow controller pins in hardware
13 - rts-gpios: RTS pin for USP-based UART if uart-has-rtscts is true
14 - cts-gpios: CTS pin for USP-based UART if uart-has-rtscts is true
18 uart0: uart@b0050000 {
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| D | samsung_uart.txt | 1 * Samsung's UART Controller
3 The Samsung's UART controller is used for interfacing SoC with serial
7 - compatible: should be one of following:
8 - "samsung,exynos4210-uart" - Exynos4210 SoC,
9 - "samsung,s3c2410-uart" - compatible with ports present on S3C2410 SoC,
10 - "samsung,s3c2412-uart" - compatible with ports present on S3C2412 SoC,
11 - "samsung,s3c2440-uart" - compatible with ports present on S3C2440 SoC,
12 - "samsung,s3c6400-uart" - compatible with ports present on S3C6400 SoC,
13 - "samsung,s5pv210-uart" - compatible with ports present on S5PV210 SoC.
15 - reg: base physical address of the controller and length of memory mapped
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/serial/ |
| D | sirf-uart.txt | 4 - compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart",
5 "sirf,atlas7-uart" or "sirf,atlas7-usp-uart".
6 - reg : Offset and length of the register set for the device
7 - interrupts : Should contain uart interrupt
8 - fifosize : Should define hardware rx/tx fifo size
9 - clocks : Should contain uart clock number
12 - uart-has-rtscts: we have hardware flow controller pins in hardware
13 - rts-gpios: RTS pin for USP-based UART if uart-has-rtscts is true
14 - cts-gpios: CTS pin for USP-based UART if uart-has-rtscts is true
18 uart0: uart@b0050000 {
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| D | samsung_uart.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C, S5P and Exynos SoC UART Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
15 node, according to serialN format, where N is the port number (non-negative
21 - enum:
22 - samsung,s3c2410-uart
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| /kernel/linux/linux-4.19/drivers/tty/serial/ |
| D | sirfsoc_uart.h | 1 // SPDX-License-Identifier: GPL-2.0+
16 /* hardware uart specific */
19 /* uart - usp common */
112 full_bit = ilog2(port->fifosize); in uart_usp_ff_full_mask()
120 empty_bit = ilog2(port->fifosize) + 1; in uart_usp_ff_empty_mask()
185 .port_name = "sirfsoc-uart",
259 /* uart io ctrl */
286 /* UART FIFO Register */
329 /* USP-UART Common */
336 #define SIRFUART_FIFO_THD(port) (port->fifosize >> 1)
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| D | samsung.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
12 * UERSTAT register in the UART blocks, and keeps marking some of the
21 * BJD, 04-Nov-2004
29 #include <linux/dma-mapping.h>
74 /* UART name and device definitions */
86 #define tx_enabled(port) ((port)->unused[0])
87 #define rx_enabled(port) ((port)->unused[1])
101 return to_platform_device(port->dev)->name; in s3c24xx_serial_portname()
116 return to_ourport(port)->info->type == PORT_S3C6400; in s3c24xx_serial_has_interrupt_mask()
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| D | sccnxp.c | 1 // SPDX-License-Identifier: GPL-2.0+
27 #include <linux/platform_data/serial-sccnxp.h>
30 #define SCCNXP_NAME "uart-sccnxp"
92 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
93 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
105 unsigned int fifosize; member
109 struct uart_driver uart; member
139 .fifosize = 3,
149 .fifosize = 3,
159 .fifosize = 3,
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| D | samsung.h | 1 // SPDX-License-Identifier: GPL-2.0
8 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
17 unsigned int fifosize; member
29 /* uart port features */
33 /* uart controls */
40 unsigned int fifosize[CONFIG_SERIAL_SAMSUNG_UARTS]; member
109 #define portaddr(port, reg) ((port)->membase + (reg))
111 ((unsigned long *)(unsigned long)((port)->membase + (reg)))
119 /* Byte-order aware bit setting/clearing functions. */
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| D | apbuart.c | 1 // SPDX-License-Identifier: GPL-2.0
10 * Copyright (C) 2008 Gilead Kutnick <kutnickg@zin-tech.com>
78 unsigned int max_chars = port->fifosize; in apbuart_rx_chars()
82 while (UART_RX_DATA(status) && (max_chars--)) { in apbuart_rx_chars()
87 port->icount.rx++; in apbuart_rx_chars()
95 port->icount.brk++; in apbuart_rx_chars()
99 port->icount.parity++; in apbuart_rx_chars()
101 port->icount.frame++; in apbuart_rx_chars()
104 port->icount.overrun++; in apbuart_rx_chars()
106 rsr &= port->read_status_mask; in apbuart_rx_chars()
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| /kernel/linux/linux-5.10/drivers/tty/serial/ |
| D | sirfsoc_uart.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
16 /* hardware uart specific */
19 /* uart - usp common */
112 full_bit = ilog2(port->fifosize); in uart_usp_ff_full_mask()
120 empty_bit = ilog2(port->fifosize) + 1; in uart_usp_ff_empty_mask()
186 .port_name = "sirfsoc-uart",
260 /* uart io ctrl */
287 /* UART FIFO Register */
330 /* USP-UART Common */
337 #define SIRFUART_FIFO_THD(port) (port->fifosize >> 1)
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| D | samsung_tty.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
12 * UERSTAT register in the UART blocks, and keeps marking some of the
21 * BJD, 04-Nov-2004
25 #include <linux/dma-mapping.h>
45 /* UART name and device definitions */
62 unsigned int fifosize; member
74 /* uart port features */
82 unsigned int fifosize[CONFIG_SERIAL_SAMSUNG_UARTS]; member
153 #define portaddr(port, reg) ((port)->membase + (reg))
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| D | sccnxp.c | 1 // SPDX-License-Identifier: GPL-2.0+
24 #include <linux/platform_data/serial-sccnxp.h>
27 #define SCCNXP_NAME "uart-sccnxp"
93 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
94 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
106 unsigned int fifosize; member
112 struct uart_driver uart; member
142 .fifosize = 3,
153 .fifosize = 3,
164 .fifosize = 3,
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| D | apbuart.c | 1 // SPDX-License-Identifier: GPL-2.0
10 * Copyright (C) 2008 Gilead Kutnick <kutnickg@zin-tech.com>
74 unsigned int max_chars = port->fifosize; in apbuart_rx_chars()
78 while (UART_RX_DATA(status) && (max_chars--)) { in apbuart_rx_chars()
83 port->icount.rx++; in apbuart_rx_chars()
91 port->icount.brk++; in apbuart_rx_chars()
95 port->icount.parity++; in apbuart_rx_chars()
97 port->icount.frame++; in apbuart_rx_chars()
100 port->icount.overrun++; in apbuart_rx_chars()
102 rsr &= port->read_status_mask; in apbuart_rx_chars()
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| D | msm_serial.c | 1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/dma-mapping.h>
171 struct uart_port uart; member
183 #define UART_TO_MSM(uart_port) container_of(uart_port, struct msm_port, uart)
188 writel_relaxed(val, port->membase + off); in msm_write()
194 return readl_relaxed(port->membase + off); in msm_read()
206 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxo()
218 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxoby4()
229 if (msm_port->is_uartdm) in msm_serial_set_mnd_regs()
232 if (port->uartclk == 19200000) in msm_serial_set_mnd_regs()
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | prima2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&intc>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
22 d-cache-line-size = <32>;
23 i-cache-line-size = <32>;
24 d-cache-size = <32768>;
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| D | atlas6.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&intc>;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 d-cache-line-size = <32>;
21 i-cache-line-size = <32>;
22 d-cache-size = <32768>;
23 i-cache-size = <32768>;
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | prima2.dtsi | 12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
24 d-cache-line-size = <32>;
25 i-cache-line-size = <32>;
26 d-cache-size = <32768>;
27 i-cache-size = <32768>;
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| D | atlas6.dtsi | 12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 d-cache-line-size = <32>;
23 i-cache-line-size = <32>;
24 d-cache-size = <32768>;
25 i-cache-size = <32768>;
27 timebase-frequency = <0>;
[all …]
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