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Searched full:uart3_gate (Results 1 – 12 of 12) sorted by relevance

/kernel/linux/linux-5.10/drivers/clk/imx/
Dclk-imx31.c46 sim_gate, ect_gate, usb_gate, kpp_gate, ipu_gate, uart3_gate, enumerator
58 &clk[uart3_gate],
114 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "per", base + MXC_CCM_CGR1, 24); in _mx31_clocks_init()
Dclk-imx35.c78 /* 70 */ uart1_gate, uart2_gate, uart3_gate, usbotg_gate, wdog_gate, enumerator
209 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "uart_div", base + MX35_CCM_CGR2, 20); in _mx35_clocks_init()
Dclk-imx1.c59 clk[IMX1_CLK_UART3_GATE] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6); in mx1_clocks_init_dt()
/kernel/linux/linux-4.19/drivers/clk/imx/
Dclk-imx31.c58 sim_gate, ect_gate, usb_gate, kpp_gate, ipu_gate, uart3_gate, enumerator
70 &clk[uart3_gate],
126 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "per", base + MXC_CCM_CGR1, 24); in _mx31_clocks_init()
190 clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2"); in mx31_clocks_init()
Dclk-imx35.c82 /* 70 */ uart1_gate, uart2_gate, uart3_gate, usbotg_gate, wdog_gate, enumerator
93 &clk[uart3_gate],
221 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "uart_div", base + MX35_CCM_CGR2, 20); in _mx35_clocks_init()
296 clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2"); in mx35_clocks_init()
Dclk-imx1.c71 clk[IMX1_CLK_UART3_GATE] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6); in mx1_clocks_init_dt()
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/
Dimx31-clock.txt63 uart3_gate 48
Dimx35-clock.txt87 uart3_gate 72
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dimx35-clock.yaml91 uart3_gate 72
Dimx31-clock.yaml67 uart3_gate 48
/kernel/linux/linux-4.19/drivers/clk/nxp/
Dclk-lpc32xx.c1299 LPC32XX_DEFINE_GATE(UART3_GATE, UART_CLK_CTRL, 0, 0),
1300 LPC32XX_DEFINE_COMPOSITE(UART3, UART3_MUX, UART3_DIV, UART3_GATE),
/kernel/linux/linux-5.10/drivers/clk/nxp/
Dclk-lpc32xx.c1293 LPC32XX_DEFINE_GATE(UART3_GATE, UART_CLK_CTRL, 0, 0),
1294 LPC32XX_DEFINE_COMPOSITE(UART3, UART3_MUX, UART3_DIV, UART3_GATE),