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/kernel/linux/linux-4.19/drivers/input/rmi4/
Drmi_f34v7.c31 f34->fn->fd.data_base_addr + f34->v7.off.flash_status, in rmi_f34v7_read_flash_status()
40 f34->v7.in_bl_mode = status >> 7; in rmi_f34v7_read_flash_status()
41 f34->v7.flash_status = status & 0x1f; in rmi_f34v7_read_flash_status()
43 if (f34->v7.flash_status != 0x00) { in rmi_f34v7_read_flash_status()
45 __func__, f34->v7.flash_status, f34->v7.command); in rmi_f34v7_read_flash_status()
49 f34->fn->fd.data_base_addr + f34->v7.off.flash_cmd, in rmi_f34v7_read_flash_status()
58 f34->v7.command = command; in rmi_f34v7_read_flash_status()
69 if (!wait_for_completion_timeout(&f34->v7.cmd_done, timeout)) { in rmi_f34v7_wait_for_idle()
128 base + f34->v7.off.partition_id, in rmi_f34v7_write_command_single_transaction()
177 f34->v7.command = command; in rmi_f34v7_write_command()
[all …]
/kernel/linux/linux-5.10/drivers/input/rmi4/
Drmi_f34v7.c28 f34->fn->fd.data_base_addr + f34->v7.off.flash_status, in rmi_f34v7_read_flash_status()
37 f34->v7.in_bl_mode = status >> 7; in rmi_f34v7_read_flash_status()
38 f34->v7.flash_status = status & 0x1f; in rmi_f34v7_read_flash_status()
40 if (f34->v7.flash_status != 0x00) { in rmi_f34v7_read_flash_status()
42 __func__, f34->v7.flash_status, f34->v7.command); in rmi_f34v7_read_flash_status()
46 f34->fn->fd.data_base_addr + f34->v7.off.flash_cmd, in rmi_f34v7_read_flash_status()
55 f34->v7.command = command; in rmi_f34v7_read_flash_status()
66 if (!wait_for_completion_timeout(&f34->v7.cmd_done, timeout)) { in rmi_f34v7_wait_for_idle()
125 base + f34->v7.off.partition_id, in rmi_f34v7_write_command_single_transaction()
174 f34->v7.command = command; in rmi_f34v7_write_command()
[all …]
/kernel/linux/linux-4.19/drivers/media/platform/s5p-mfc/
Ds5p_mfc_opr.h45 void __iomem *dis_shared_mem_addr;/* only v7 */
67 void __iomem *d_min_num_dis;/* only v7 */
68 void __iomem *d_min_first_dis_size;/* only v7 */
69 void __iomem *d_min_second_dis_size;/* only v7 */
70 void __iomem *d_min_third_dis_size;/* only v7 */
71 void __iomem *d_post_filter_luma_dpb0;/* v7 and v8 */
72 void __iomem *d_post_filter_luma_dpb1;/* v7 and v8 */
73 void __iomem *d_post_filter_luma_dpb2;/* only v7 */
74 void __iomem *d_post_filter_chroma_dpb0;/* v7 and v8 */
75 void __iomem *d_post_filter_chroma_dpb1;/* v7 and v8 */
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/s5p-mfc/
Ds5p_mfc_opr.h42 void __iomem *dis_shared_mem_addr;/* only v7 */
64 void __iomem *d_min_num_dis;/* only v7 */
65 void __iomem *d_min_first_dis_size;/* only v7 */
66 void __iomem *d_min_second_dis_size;/* only v7 */
67 void __iomem *d_min_third_dis_size;/* only v7 */
68 void __iomem *d_post_filter_luma_dpb0;/* v7 and v8 */
69 void __iomem *d_post_filter_luma_dpb1;/* v7 and v8 */
70 void __iomem *d_post_filter_luma_dpb2;/* only v7 */
71 void __iomem *d_post_filter_chroma_dpb0;/* v7 and v8 */
72 void __iomem *d_post_filter_chroma_dpb1;/* v7 and v8 */
[all …]
/kernel/linux/linux-4.19/arch/arm64/crypto/
Dcrct10dif-ce-core.S123 CPU_LE( rev64 v7.16b, v7.16b )
132 CPU_LE( ext v7.16b, v7.16b, v7.16b, #8 )
179 fold64 v6, v7
218 eor v7.16b, v7.16b, v8.16b
219 eor v7.16b, v7.16b, \reg\().16b
236 // now we have 16+y bytes left to reduce. 16 Bytes is in register v7
241 pmull v8.1q, v7.1d, v10.1d
242 pmull2 v7.1q, v7.2d, v10.2d
243 eor v7.16b, v7.16b, v8.16b
248 eor v7.16b, v7.16b, v0.16b
[all …]
Daes-modes.S169 ld1 {v7.16b}, [x24] /* get iv */
181 eor v0.16b, v0.16b, v7.16b
183 ld1 {v7.16b}, [x20], #16 /* reload 1 ct block */
187 st1 {v7.16b}, [x24] /* return iv */
197 eor v0.16b, v0.16b, v7.16b /* xor with iv => pt */
198 mov v7.16b, v1.16b /* ct is next iv */
203 st1 {v7.16b}, [x24] /* return iv */
236 dup v7.4s, w6
238 add v7.4s, v7.4s, v8.4s
240 rev32 v8.16b, v7.16b
[all …]
Daes-neonbs-core.S387 ld1 {v7.4s}, [x1], #16 // load round 0 key
404 tbl v7.16b ,{v17.16b}, v16.16b
407 cmtst v0.16b, v7.16b, v8.16b
408 cmtst v1.16b, v7.16b, v9.16b
409 cmtst v2.16b, v7.16b, v10.16b
410 cmtst v3.16b, v7.16b, v11.16b
411 cmtst v4.16b, v7.16b, v12.16b
412 cmtst v5.16b, v7.16b, v13.16b
413 cmtst v6.16b, v7.16b, v14.16b
414 cmtst v7.16b, v7.16b, v15.16b
[all …]
Dchacha20-neon-core.S108 ld1 {v4.16b-v7.16b}, [x2]
124 eor v3.16b, v3.16b, v7.16b
151 ld4r { v4.4s- v7.4s}, [x4], #16
168 add v3.4s, v3.4s, v7.4s
192 eor v19.16b, v7.16b, v11.16b
197 shl v7.4s, v19.4s, #12
202 sri v7.4s, v19.4s, #20
211 add v3.4s, v3.4s, v7.4s
235 eor v19.16b, v7.16b, v11.16b
240 shl v7.4s, v19.4s, #7
[all …]
Dsha256-core.S_shipped1093 ld1 {v4.16b-v7.16b},[x1],#64
1099 rev32 v7.16b,v7.16b
1108 .inst 0x5e0760c4 //sha256su1 v4.16b,v6.16b,v7.16b
1115 .inst 0x5e0460e5 //sha256su1 v5.16b,v7.16b,v4.16b
1118 .inst 0x5e2828e6 //sha256su0 v6.16b,v7.16b
1124 add v17.4s,v17.4s,v7.4s
1125 .inst 0x5e282887 //sha256su0 v7.16b,v4.16b
1129 .inst 0x5e0660a7 //sha256su1 v7.16b,v5.16b,v6.16b
1136 .inst 0x5e0760c4 //sha256su1 v4.16b,v6.16b,v7.16b
1143 .inst 0x5e0460e5 //sha256su1 v5.16b,v7.16b,v4.16b
[all …]
/kernel/linux/linux-5.10/arch/arm64/crypto/
Dcrct10dif-ce-core.S282 CPU_LE( rev64 v7.16b, v7.16b )
290 CPU_LE( ext v7.16b, v7.16b, v7.16b, #8 )
305 // While >= 128 data bytes remain (not counting v0-v7), fold the 128
306 // bytes v0-v7 into them, storing the result back into v0-v7.
311 fold_32_bytes \p, v6, v7
316 // Now fold the 112 bytes in v0-v6 into the 16 bytes in v7.
325 fold_16_bytes \p, v3, v7, 1
328 fold_16_bytes \p, v5, v7, 1
330 fold_16_bytes \p, v6, v7
333 // (not counting v7), following the previous extra subtraction by 128.
[all …]
Daes-neonbs-core.S384 ld1 {v7.4s}, [x1], #16 // load round 0 key
401 tbl v7.16b ,{v17.16b}, v16.16b
404 cmtst v0.16b, v7.16b, v8.16b
405 cmtst v1.16b, v7.16b, v9.16b
406 cmtst v2.16b, v7.16b, v10.16b
407 cmtst v3.16b, v7.16b, v11.16b
408 cmtst v4.16b, v7.16b, v12.16b
409 cmtst v5.16b, v7.16b, v13.16b
410 cmtst v6.16b, v7.16b, v14.16b
411 cmtst v7.16b, v7.16b, v15.16b
[all …]
Dchacha-neon-core.S124 ld1 {v4.16b-v7.16b}, [x2]
140 eor v3.16b, v3.16b, v7.16b
217 ld4r { v4.4s- v7.4s}, [x8], #16
228 mov a7, v7.s[0]
252 add v3.4s, v3.4s, v7.4s
292 eor v19.16b, v7.16b, v11.16b
298 shl v7.4s, v19.4s, #12
306 sri v7.4s, v19.4s, #20
319 add v3.4s, v3.4s, v7.4s
359 eor v19.16b, v7.16b, v11.16b
[all …]
Dsha256-core.S_shipped1093 ld1 {v4.16b-v7.16b},[x1],#64
1099 rev32 v7.16b,v7.16b
1108 .inst 0x5e0760c4 //sha256su1 v4.16b,v6.16b,v7.16b
1115 .inst 0x5e0460e5 //sha256su1 v5.16b,v7.16b,v4.16b
1118 .inst 0x5e2828e6 //sha256su0 v6.16b,v7.16b
1124 add v17.4s,v17.4s,v7.4s
1125 .inst 0x5e282887 //sha256su0 v7.16b,v4.16b
1129 .inst 0x5e0660a7 //sha256su1 v7.16b,v5.16b,v6.16b
1136 .inst 0x5e0760c4 //sha256su1 v4.16b,v6.16b,v7.16b
1143 .inst 0x5e0460e5 //sha256su1 v5.16b,v7.16b,v4.16b
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/amd/display/dc/inc/
Dreg_helper.h105 f5, v5, f6, v6, f7, v7) \ argument
113 FN(reg, f7), v7)
116 f5, v5, f6, v6, f7, v7, f8, v8) \ argument
124 FN(reg, f7), v7,\
128 v5, f6, v6, f7, v7, f8, v8, f9, v9) \ argument
136 FN(reg, f7), v7, \
141 v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \ argument
149 FN(reg, f7), v7, \
195 #define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ argument
203 FN(reg_name, f7), v7)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/
Dreg_helper.h105 f5, v5, f6, v6, f7, v7) \ argument
113 FN(reg, f7), v7)
116 f5, v5, f6, v6, f7, v7, f8, v8) \ argument
124 FN(reg, f7), v7,\
128 v5, f6, v6, f7, v7, f8, v8, f9, v9) \ argument
136 FN(reg, f7), v7, \
141 v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \ argument
149 FN(reg, f7), v7, \
195 #define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ argument
203 FN(reg_name, f7), v7)
[all …]
/kernel/linux/linux-4.19/arch/powerpc/crypto/
Dcrc32-vpmsum_core.S163 /* zero v0-v7 which will contain our checksums */
171 vxor v7,v7,v7
306 vxor v7,v7,v15
348 vxor v7,v7,v15
361 vxor v7,v7,v15
377 vsldoi v7,v7,zeroes,4
407 vxor v23,v7,v15
436 lvx v7,off112,r3
446 VPMSUMW(v7,v23,v7)
504 vxor v6,v6,v7
[all …]
/kernel/linux/linux-5.10/arch/powerpc/crypto/
Dcrc32-vpmsum_core.S159 /* zero v0-v7 which will contain our checksums */
167 vxor v7,v7,v7
302 vxor v7,v7,v15
344 vxor v7,v7,v15
357 vxor v7,v7,v15
373 vsldoi v7,v7,zeroes,4
403 vxor v23,v7,v15
432 lvx v7,off112,r3
442 VPMSUMW(v7,v23,v7)
500 vxor v6,v6,v7
[all …]
/kernel/linux/linux-4.19/arch/arm/mm/
DMakefile13 obj-$(CONFIG_ARM_MPU) += pmsa-v7.o pmsa-v8.o
40 obj-$(CONFIG_CPU_PABRT_V7) += pabort-v7.o
46 obj-$(CONFIG_CPU_CACHE_V7) += cache-v7.o
52 AFLAGS_cache-v7.o :=-Wa,-march=armv7-a
71 obj-$(CONFIG_CPU_TLB_V7) += tlb-v7.o
75 AFLAGS_tlb-v7.o :=-Wa,-march=armv7-a
100 obj-$(CONFIG_CPU_V7) += proc-v7.o proc-v7-bugs.o
104 AFLAGS_proc-v7.o :=-Wa,-march=armv7-a
Dcache-tauros2.c32 * When Tauros2 is used on a CPU that supports the v7 hierarchical
33 * cache operations, the cache handling code in proc-v7.S takes care
37 * being used on a pre-v7 CPU, and we only need to build support for
39 * configured to support a pre-v7 CPU.
239 * Check whether this CPU has support for the v7 hierarchical in tauros2_internal_init()
240 * cache ops. (PJ4 is in its v7 personality mode if the MMFR3 in tauros2_internal_init()
241 * register indicates support for the v7 hierarchical cache in tauros2_internal_init()
245 * implement the v7 cache ops but are only ARMv6 CPUs (due to in tauros2_internal_init()
/kernel/linux/linux-5.10/arch/arm/mm/
DMakefile14 obj-$(CONFIG_ARM_MPU) += pmsa-v7.o pmsa-v8.o
42 obj-$(CONFIG_CPU_PABRT_V7) += pabort-v7.o
48 obj-$(CONFIG_CPU_CACHE_V7) += cache-v7.o
54 AFLAGS_cache-v7.o :=-Wa,-march=armv7-a
73 obj-$(CONFIG_CPU_TLB_V7) += tlb-v7.o
77 AFLAGS_tlb-v7.o :=-Wa,-march=armv7-a
102 obj-$(CONFIG_CPU_V7) += proc-v7.o proc-v7-bugs.o
106 AFLAGS_proc-v7.o :=-Wa,-march=armv7-a
Dcache-tauros2.c32 * When Tauros2 is used on a CPU that supports the v7 hierarchical
33 * cache operations, the cache handling code in proc-v7.S takes care
37 * being used on a pre-v7 CPU, and we only need to build support for
39 * configured to support a pre-v7 CPU.
239 * Check whether this CPU has support for the v7 hierarchical in tauros2_internal_init()
240 * cache ops. (PJ4 is in its v7 personality mode if the MMFR3 in tauros2_internal_init()
241 * register indicates support for the v7 hierarchical cache in tauros2_internal_init()
245 * implement the v7 cache ops but are only ARMv6 CPUs (due to in tauros2_internal_init()
/kernel/linux/linux-4.19/arch/unicore32/lib/
Dbacktrace.S119 .Ldumpstm: stm.w (instr, reg, stack, v7, lr), [sp-]
123 mov v7, #0
131 add v7, v7, #1
132 cxor.a v7, #6
133 cmoveq v7, #1
150 cxor.a v7, #0
154 201: ldm.w (instr, reg, stack, v7, pc), [sp]+
/kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/
Darmada-3720-espressobin-v7-emmc.dts3 * Device Tree file for Globalscale Marvell ESPRESSOBin Board V7 with eMMC
19 model = "Globalscale Marvell ESPRESSOBin Board V7 (eMMC)";
20 compatible = "globalscale,espressobin-v7-emmc", "globalscale,espressobin-v7",
Darmada-3720-espressobin-v7.dts3 * Device Tree file for Globalscale Marvell ESPRESSOBin Board V7
19 model = "Globalscale Marvell ESPRESSOBin Board V7";
20 compatible = "globalscale,espressobin-v7", "globalscale,espressobin",
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/
Dbrcm,brcmnand.txt21 string, like "brcm,brcmnand-v7.0"
30 brcm,brcmnand-v7.0
31 brcm,brcmnand-v7.1
32 brcm,brcmnand-v7.2
33 brcm,brcmnand-v7.3
56 v7.0. Use this property to describe the rare
132 compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand";

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