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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/
Darm,vic.txt5 nested or have the outputs wire-OR'd together.
9 - compatible : should be one of
10 "arm,pl190-vic"
11 "arm,pl192-vic"
12 - interrupt-controller : Identifies the node as an interrupt controller
13 - #interrupt-cells : The number of cells to define the interrupts. Must be 1 as
16 - reg : The register bank for the VIC.
20 - interrupts : Interrupt source for parent controllers if the VIC is nested.
21 - valid-mask : A one cell big bit mask of valid interrupt sources. Each bit
24 clear means otherwise. If unspecified, defaults to all valid.
[all …]
Darm,versatile-fpga-irq.txt9 - compatible: "arm,versatile-fpga-irq" or "oxsemi,ox810se-rps-irq"
10 - interrupt-controller: Identifies the node as an interrupt controller
11 - #interrupt-cells: The number of cells to define the interrupts. Must be 1
14 - reg: The register bank for the FPGA interrupt controller.
15 - clear-mask: a u32 number representing the mask written to clear all IRQs
17 - valid-mask: a u32 number representing a bit mask determining which of
18 the interrupts are valid. Unconnected/unused lines are set to 0, and
25 compatible = "arm,versatile-fpga-irq";
26 #interrupt-cells = <1>;
27 interrupt-controller;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Darm,vic.txt5 nested or have the outputs wire-OR'd together.
9 - compatible : should be one of
10 "arm,pl190-vic"
11 "arm,pl192-vic"
12 - interrupt-controller : Identifies the node as an interrupt controller
13 - #interrupt-cells : The number of cells to define the interrupts. Must be 1 as
16 - reg : The register bank for the VIC.
20 - interrupts : Interrupt source for parent controllers if the VIC is nested.
21 - valid-mask : A one cell big bit mask of valid interrupt sources. Each bit
24 clear means otherwise. If unspecified, defaults to all valid.
[all …]
Darm,versatile-fpga-irq.txt9 - compatible: "arm,versatile-fpga-irq" or "oxsemi,ox810se-rps-irq"
10 - interrupt-controller: Identifies the node as an interrupt controller
11 - #interrupt-cells: The number of cells to define the interrupts. Must be 1
14 - reg: The register bank for the FPGA interrupt controller.
15 - clear-mask: a u32 number representing the mask written to clear all IRQs
17 - valid-mask: a u32 number representing a bit mask determining which of
18 the interrupts are valid. Unconnected/unused lines are set to 0, and
25 compatible = "arm,versatile-fpga-irq";
26 #interrupt-cells = <1>;
27 interrupt-controller;
[all …]
/kernel/linux/linux-5.10/net/netlabel/
Dnetlabel_addrlist.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Author: Paul Moore <paul@paul-moore.com>
14 * (c) Copyright Hewlett-Packard Development Company, L.P., 2008
27 * struct netlbl_af4list - NetLabel IPv4 address list
29 * @mask: IPv4 address mask
30 * @valid: valid flag
35 __be32 mask; member
37 u32 valid; member
42 * struct netlbl_af6list - NetLabel IPv6 address list
44 * @mask: IPv6 address mask
[all …]
Dnetlabel_addrlist.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * Author: Paul Moore <paul@paul-moore.com>
14 * (c) Copyright Hewlett-Packard Development Company, L.P., 2008
36 * netlbl_af4list_search - Search for a matching IPv4 address entry
52 if (iter->valid && (addr & iter->mask) == iter->addr) in netlbl_af4list_search()
59 * netlbl_af4list_search_exact - Search for an exact IPv4 address entry
61 * @mask: IPv4 address mask
71 __be32 mask, in netlbl_af4list_search_exact() argument
77 if (iter->valid && iter->addr == addr && iter->mask == mask) in netlbl_af4list_search_exact()
86 * netlbl_af6list_search - Search for a matching IPv6 address entry
[all …]
/kernel/linux/linux-4.19/net/netlabel/
Dnetlabel_addrlist.h9 * Author: Paul Moore <paul@paul-moore.com>
14 * (c) Copyright Hewlett-Packard Development Company, L.P., 2008
41 * struct netlbl_af4list - NetLabel IPv4 address list
43 * @mask: IPv4 address mask
44 * @valid: valid flag
49 __be32 mask; member
51 u32 valid; member
56 * struct netlbl_af6list - NetLabel IPv6 address list
58 * @mask: IPv6 address mask
59 * @valid: valid flag
[all …]
Dnetlabel_addrlist.c9 * Author: Paul Moore <paul@paul-moore.com>
14 * (c) Copyright Hewlett-Packard Development Company, L.P., 2008
50 * netlbl_af4list_search - Search for a matching IPv4 address entry
66 if (iter->valid && (addr & iter->mask) == iter->addr) in netlbl_af4list_search()
73 * netlbl_af4list_search_exact - Search for an exact IPv4 address entry
75 * @mask: IPv4 address mask
85 __be32 mask, in netlbl_af4list_search_exact() argument
91 if (iter->valid && iter->addr == addr && iter->mask == mask) in netlbl_af4list_search_exact()
100 * netlbl_af6list_search - Search for a matching IPv6 address entry
116 if (iter->valid && in netlbl_af6list_search()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/apm/xgene/
Dxgene_enet_cle.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Applied Micro X-Gene SoC Ethernet Classifier structures
27 if (pdata->enet_id == XGENE_ENET1) { in xgene_cle_idt_to_hw()
41 buf[0] = SET_VAL(CLE_DROP, dbptr->drop); in xgene_cle_dbptr_to_hw()
42 buf[4] = SET_VAL(CLE_FPSEL, dbptr->fpsel) | in xgene_cle_dbptr_to_hw()
43 SET_VAL(CLE_NFPSEL, dbptr->nxtfpsel) | in xgene_cle_dbptr_to_hw()
44 SET_VAL(CLE_DSTQIDL, dbptr->dstqid); in xgene_cle_dbptr_to_hw()
46 buf[5] = SET_VAL(CLE_DSTQIDH, (u32)dbptr->dstqid >> CLE_DSTQIDL_LEN) | in xgene_cle_dbptr_to_hw()
47 SET_VAL(CLE_PRIORITY, dbptr->cle_priority); in xgene_cle_dbptr_to_hw()
55 buf[j++] = SET_VAL(CLE_TYPE, kn->node_type); in xgene_cle_kn_to_hw()
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/apm/xgene/
Dxgene_enet_cle.c1 /* Applied Micro X-Gene SoC Ethernet Classifier structures
39 if (pdata->enet_id == XGENE_ENET1) { in xgene_cle_idt_to_hw()
53 buf[0] = SET_VAL(CLE_DROP, dbptr->drop); in xgene_cle_dbptr_to_hw()
54 buf[4] = SET_VAL(CLE_FPSEL, dbptr->fpsel) | in xgene_cle_dbptr_to_hw()
55 SET_VAL(CLE_NFPSEL, dbptr->nxtfpsel) | in xgene_cle_dbptr_to_hw()
56 SET_VAL(CLE_DSTQIDL, dbptr->dstqid); in xgene_cle_dbptr_to_hw()
58 buf[5] = SET_VAL(CLE_DSTQIDH, (u32)dbptr->dstqid >> CLE_DSTQIDL_LEN) | in xgene_cle_dbptr_to_hw()
59 SET_VAL(CLE_PRIORITY, dbptr->cle_priority); in xgene_cle_dbptr_to_hw()
67 buf[j++] = SET_VAL(CLE_TYPE, kn->node_type); in xgene_cle_kn_to_hw()
68 for (i = 0; i < kn->num_keys; i++) { in xgene_cle_kn_to_hw()
[all …]
/kernel/linux/linux-4.19/drivers/irqchip/
Dirq-versatile-fpga.c1 // SPDX-License-Identifier: GPL-2.0
3 * Support for Versatile FPGA-based IRQ controllers
10 #include <linux/irqchip/versatile-fpga.h>
35 * struct fpga_irq_data - irq data container for the FPGA IRQ controller
39 * @valid: mask for valid IRQs on this controller
45 u32 valid; member
57 u32 mask = 1 << d->hwirq; in fpga_irq_mask() local
59 writel(mask, f->base + IRQ_ENABLE_CLEAR); in fpga_irq_mask()
65 u32 mask = 1 << d->hwirq; in fpga_irq_unmask() local
67 writel(mask, f->base + IRQ_ENABLE_SET); in fpga_irq_unmask()
[all …]
/kernel/linux/linux-5.10/drivers/irqchip/
Dirq-versatile-fpga.c1 // SPDX-License-Identifier: GPL-2.0
3 * Support for Versatile FPGA-based IRQ controllers
10 #include <linux/irqchip/versatile-fpga.h>
35 * struct fpga_irq_data - irq data container for the FPGA IRQ controller
39 * @valid: mask for valid IRQs on this controller
45 u32 valid; member
57 u32 mask = 1 << d->hwirq; in fpga_irq_mask() local
59 writel(mask, f->base + IRQ_ENABLE_CLEAR); in fpga_irq_mask()
65 u32 mask = 1 << d->hwirq; in fpga_irq_unmask() local
67 writel(mask, f->base + IRQ_ENABLE_SET); in fpga_irq_unmask()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/aquantia/atlantic/macsec/
Dmacsec_struct.h1 /* SPDX-License-Identifier: GPL-2.0-only */
21 /*! The match mask is per-nibble. 0 means don't care, i.e. every value
68 /*! This is to specify the 40bit SNAP header if the SNAP header's mask
72 /*! This is to specify the 24bit LLC header if the LLC header's mask is
122 /*! Mask is per-byte.
132 * 1: enable comparison of extracted VLAN Valid field.
135 /*! This is bit mask to enable comparison the 8 bit TCI field,
142 /*! Mask is per-byte.
151 /*! Mask is per-byte.
156 /*! Mask is per-byte.
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/pensando/ionic/
Dionic_regs.h1 /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */
2 /* Copyright (c) 2018-2019 Pensando Systems, Inc. All rights reserved. */
9 /** struct ionic_intr - interrupt control register set.
11 * @mask: interrupt mask value.
13 * @mask_assert: interrupt mask value on assert.
18 u32 mask; member
28 /** enum ionic_intr_mask_vals - valid values for mask and mask_assert.
30 * @IONIC_INTR_MASK_SET: mask interrupt.
37 /** enum ionic_intr_credits_bits - bitwise composition of credits values.
38 * @IONIC_INTR_CRED_COUNT: bit mask of credit count, no shift needed.
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Ds3c6400.dtsi1 // SPDX-License-Identifier: GPL-2.0
23 valid-mask = <0xfffffe1f>;
24 valid-wakeup-mask = <0x00200004>;
28 valid-mask = <0xffffffff>;
29 valid-wakeup-mask = <0x53020000>;
33 clocks: clock-controller@7e00f000 {
34 compatible = "samsung,s3c6400-clock";
36 #clock-cells = <1>;
Ds3c6410.dtsi1 // SPDX-License-Identifier: GPL-2.0
27 valid-mask = <0xffffff7f>;
28 valid-wakeup-mask = <0x00200004>;
32 valid-mask = <0xffffffff>;
33 valid-wakeup-mask = <0x53020000>;
37 clocks: clock-controller@7e00f000 {
38 compatible = "samsung,s3c6410-clock";
40 #clock-cells = <1>;
44 compatible = "samsung,s3c2440-i2c";
46 interrupt-parent = <&vic0>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Ds3c6400.dtsi1 // SPDX-License-Identifier: GPL-2.0
23 valid-mask = <0xfffffe1f>;
24 valid-wakeup-mask = <0x00200004>;
28 valid-mask = <0xffffffff>;
29 valid-wakeup-mask = <0x53020000>;
33 clocks: clock-controller@7e00f000 {
34 compatible = "samsung,s3c6400-clock";
36 #clock-cells = <1>;
Ds3c6410.dtsi1 // SPDX-License-Identifier: GPL-2.0
27 valid-mask = <0xffffff7f>;
28 valid-wakeup-mask = <0x00200004>;
32 valid-mask = <0xffffffff>;
33 valid-wakeup-mask = <0x53020000>;
37 clocks: clock-controller@7e00f000 {
38 compatible = "samsung,s3c6410-clock";
40 #clock-cells = <1>;
44 compatible = "samsung,s3c2440-i2c";
46 interrupt-parent = <&vic0>;
[all …]
/kernel/linux/linux-5.10/drivers/net/ipa/
Dipa_smp2p.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2019-2020 Linaro Ltd.
34 * whether the clock is enabled using two SMP2P state bits--one to
36 * clock state bit is valid. The modem will poll the valid bit until it
44 * struct ipa_smp2p - IPA SMP2P information
46 * @valid_state: SMEM state indicating enabled state is valid
48 * @valid_bit: Valid bit in 32-bit SMEM state mask
49 * @enabled_bit: Enabled bit in 32-bit SMEM state mask
50 * @enabled_bit: Enabled bit in 32-bit SMEM state mask
[all …]
/kernel/liteos_m/kernel/include/
Dlos_event.h2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
68 * Bit 25 of the event mask cannot be set to an event because it is set to an error code.
72 * Solution: Set bits excluding bit 25 of the event mask to events.
81 …* Solution: Increase the waiting time for event reading, or make another task write a mask for the…
87 …* Event reading error code: The EVENTMASK input parameter value is valid. The input parameter valu…
91 * Solution: Pass in a valid EVENTMASK value.
114 * Solution: Pass in a valid uwFlags value.
160 * Event reading error code: The event is being read in a system-level task.
163 * Solution: Read the event in a valid task.
[all …]
/kernel/liteos_a/kernel/include/
Dlos_event.h2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
69 * Bit 25 of the event mask cannot be set to an event because it is set to an error code.
73 * Solution: Set bits excluding bit 25 of the event mask to events.
83 …* Solution: Increase the waiting time for event reading, or make another task write a mask for the…
89 …* Event reading error code: The EVENTMASK input parameter value is valid. The input parameter valu…
93 * Solution: Pass in a valid EVENTMASK value.
116 * Solution: Pass in a valid flag value.
142 * Event reading error code: The event is being read in system-level task.
165 UINT32 uwEventID; /**< Event mask in the event control block,
[all …]
/kernel/linux/linux-4.19/include/linux/
Dregmap.h47 * struct reg_default - Default value for a register.
61 * struct reg_sequence - An individual write from a sequence of writes.
76 #define regmap_update_bits(map, reg, mask, val) \ argument
77 regmap_update_bits_base(map, reg, mask, val, NULL, false, false)
78 #define regmap_update_bits_async(map, reg, mask, val)\ argument
79 regmap_update_bits_base(map, reg, mask, val, NULL, true, false)
80 #define regmap_update_bits_check(map, reg, mask, val, change)\ argument
81 regmap_update_bits_base(map, reg, mask, val, change, false, false)
82 #define regmap_update_bits_check_async(map, reg, mask, val, change)\ argument
83 regmap_update_bits_base(map, reg, mask, val, change, true, false)
[all …]
/kernel/linux/linux-5.10/include/linux/
Dregmap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
48 * struct reg_default - Default value for a register.
62 * struct reg_sequence - An individual write from a sequence of writes.
85 * regmap_read_poll_timeout - Poll until a condition is met or a timeout occurs
92 * tight-loops). Should be less than ~20ms since usleep_range
93 * is used (see Documentation/timers/timers-howto.rst).
96 * Returns 0 on success and -ETIMEDOUT upon a timeout or the regmap_read
112 * regmap_read_poll_timeout_atomic - Poll until a condition is met or a timeout occurs
118 * @delay_us: Time to udelay between reads in us (0 tight-loops).
120 * (see Documentation/timers/timers-howto.rst).
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-pxa/
Dmfp-pxa2xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-pxa/mfp-pxa2xx.c
13 #include <linux/gpio-pxa.h>
20 #include <mach/pxa2xx-regs.h>
21 #include "mfp-pxa2xx.h"
30 #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
39 unsigned valid : 1; member
43 unsigned int mask; /* bit mask in PWER or PKWR */ member
44 unsigned int mux_mask; /* bit mask of muxed gpio bits, 0 if no mux */
54 unsigned long gafr, mask = GPIO_bit(gpio); in __mfp_config_gpio() local
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-pxa/
Dmfp-pxa2xx.c2 * linux/arch/arm/mach-pxa/mfp-pxa2xx.c
16 #include <linux/gpio-pxa.h>
23 #include <mach/pxa2xx-regs.h>
24 #include "mfp-pxa2xx.h"
33 #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
42 unsigned valid : 1; member
46 unsigned int mask; /* bit mask in PWER or PKWR */ member
47 unsigned int mux_mask; /* bit mask of muxed gpio bits, 0 if no mux */
57 unsigned long gafr, mask = GPIO_bit(gpio); in __mfp_config_gpio() local
65 return -EINVAL; in __mfp_config_gpio()
[all …]

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